Physical Design Lead

Job Title

Physical Design Lead

Role Summary

Lead a physical design implementation team in Bangalore responsible for RTL-to-GDS delivery of high-performance IP, test chips, and chiplet designs at advanced process nodes. Work closely with SoC architects, IP teams, PD/STA engineers, and CAD/EDA vendors to achieve tape-out and signoff.

Deliver technical direction, drive convergence and signoff flows, and improve PPA and methodology across projects.

Experience Level

Senior — the role expects a seasoned physical design professional with substantial industry experience; the posting specifies a minimum of 15 years of relevant physical design experience and management of multiple tape-outs.

Responsibilities

Accountable for end-to-end backend implementation and team delivery; primary responsibilities include:

• Lead the physical design team for implementation and convergence of complex tiles and full-chip integration.
• Manage delivery from RTL to GDS, including signoff and physical verification.
• Drive timing closure, STA, and signoff activities at both block and full-chip levels.
• Oversee PnR tasks: floorplanning, placement, routing, ECOs and timing fixes.
• Collaborate with SOC architects, IP teams, PD/STA engineers, CAD group, and EDA vendors to resolve integration and closure issues.
• Track project milestones, convergence status, and tape-out readiness across the design cycle.
• Propose and drive methodology improvements to improve PPA and closure efficiency.
• Provide technical mentorship and guidance to engineering team members.

Requirements

Key must-have skills and experience; separate list for desirable skills.

• 15+ years of industry experience in physical design covering RTL-to-GDS flows, STA, physical verification, timing signoff, and tapeout delivery.
• Proven experience managing multiple (more than four) tape-outs.
• Hands-on expertise in block-level implementation (place and route), floorplanning, timing closure, and physical verification.
• Strong knowledge of sign-off flows and techniques (timing convergence, formal equivalence/LEC, IR/EM checks, low-power verification, VCLP, VSI where applicable).
• Proficiency with industry EDA tools (examples: Fusion Compiler/ICC2, PrimeTime, RedHawk/PTPX) and low-power/physical verification toolchains.
• Scripting and RTL skills: Perl/TCL/Shell/Python and Verilog/VHDL experience.
• Effective communication, cross-functional collaboration, and experience driving closures with CAD/EDA vendors.

• Experience with methodology development and driving process changes across teams.
• Prior work on advanced-node PPA optimizations and complex full-chip integrations.

Education Requirements

B.Tech, M.Tech, MS or Ph.D. in Computer Engineering, Electronics, or Electrical Engineering (or equivalent technical degree) as stated in the posting.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.