Physical Design Layout Engineer (ICE)
Design and optimize chip physical implementations including cell and block-level semi-custom layouts, FUB-level floor plans, abstract view generation, and schematic-to-layout verification. The role is on Intel's semiconductor engineering team and contributes to methodologies that improve reliability and performance.
Entry-level β 0β1 years of hands-on experience; suitable for recent graduates or candidates with internship or academic project experience.
Key day-to-day responsibilities include:
Core technical expectations and desirable skills.
Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0β1 years of hands-on experience (including internships, academic projects, coursework, or training) OR a Master's degree in Electronics, Electrical Engineering, or a related field with no prior professional experience. The posting also accepts equivalent practical experience gained through internships or projects.
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
