Physical Design Implementation and Signoff Methodology Lead & Architect

Job Title

Physical Design Implementation and Signoff Methodology Lead & Architect

Role Summary

Senior individual-contributor role owning the architecture and deployment of physical design implementation and signoff methodology across the product portfolio. Responsible for place-and-route implementation, EMIR (electromigration and IR-drop) analysis, timing signoff, and power signoff flows.

The role defines scalable flows and quality gates, drives AI/ML-enabled productivity improvements, partners with technology and EDA vendors, and mentors other engineers.

Experience Level

Senior - Principal Engineer / Senior Principal Engineer. Principal: ~12+ years of physical design experience; Senior Principal: ~15+ years. Requires a minimum of 8 years developing and deploying implementation or signoff methodology.

Responsibilities

Own end-to-end implementation and signoff methodology and architect flows that scale across multiple products and nodes.

• Define and improve PD implementation and signoff flows, standards, and quality gates (place-and-route, EMIR, timing, power).
• Set methodology strategy and deploy flows across design teams and process nodes.
• Introduce and validate AI/ML techniques for prediction, automated debug/fix recommendation, and flow orchestration.
• Partner with process/technology teams and EDA vendors to qualify next-generation methodologies.
• Lead root-cause analysis and drive resolution of complex EMIR, timing, and power signoff issues.
• Establish golden reference flows and signoff criteria to improve first-pass silicon success.
• Evaluate and qualify emerging EDA tools and AI/ML-for-EDA solutions.
• Mentor and raise the competency of design and CAD engineers in methodology and best practices.

Requirements

Must-have technical skills, tool experience, and abilities required to execute the role.

• Deep, hands-on expertise in physical design implementation and signoff methodology, especially EMIR analysis, timing signoff (STA), and power signoff.
• Demonstrated track record architecting and deploying PD methodologies across multiple tapeouts and process nodes.
• Hands-on proficiency with industry-standard tools (examples: Ansys RedHawk-SC, Synopsys PrimeTime/PrimePower/Fusion Compiler, Cadence Innovus/Voltus/Tempus or equivalent).
• Working knowledge of advanced-node physical design challenges, parasitic extraction, and reliability signoff requirements.
• AI/ML-driven mindset with experience applying predictive or ML techniques to EDA problems (prediction, optimization, flow automation).
• Scripting and automation skills (Python, Tcl) to build methodology infrastructure and integrate ML pipelines.
• Strong cross-functional collaboration and communication skills; able to influence methodology across teams and sites.
• Practical, hands-on approach comfortable with execution from early flow architecture to late-stage tapeout debugging.
• Preferred: experience defining methodology strategy across product generations, working with foundry PDKs, and publications or patents in PD/EDA or AI/ML-for-EDA.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field (explicit degree requirement listed). The posting pairs these degrees with senior experience expectations (Principal / Senior Principal levels with multi-year PD and methodology experience).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.