Physical Design Engineer (Staff / Sr. Staff)

Job Title

Physical Design Engineer (Staff / Sr. Staff)

Role Summary

Responsible for architecting, implementing, optimizing, and signing off advanced clock distribution solutions for high-performance NSP ASIC/SoC designs. The role works across physical design, timing, power, PLL, CAD, RTL, and implementation teams to meet aggressive performance, power, variation, and reliability targets on advanced technology nodes.

Experience Level

Senior-level. The posting expects extensive industry experience; typical candidates have 10+ years in ASIC/SoC physical design with significant hands-on clock implementation and timing-closure experience.

Responsibilities

Key responsibilities include:

• Own and drive clock physical-design methodology, implementation, optimization, and signoff for complex SoC/NSP designs.
• Architect and optimize clock distribution topologies (H-trees, mesh, spines) and hierarchical clocking across block and top-level designs.
• Perform detailed SPICE/transistor-level simulation and waveform analysis of critical clock structures.
• Analyze and debug clock-related timing issues: skew, insertion delay, jitter, duty-cycle distortion, slew, and variation.
• Drive clock convergence and signoff across multiple modes, process corners, voltages, temperatures, and frequencies.
• Provide technical guidance to block-level and top-level physical-design teams on clock fixes, routing, and timing/variation concerns.
• Collaborate with PLL, STA/timing, power, CAD, RTL, and implementation teams to align clock-source assumptions, jitter budgets, and signoff methodology.
• Use Synopsys PrimeTime and correlate STA, extraction, implementation, and SPICE results as needed.
• Develop and tune clock implementation recipes and automation; support ECOs during timing closure and tapeout convergence.
• Evaluate clock networks for IR-drop, electromigration, crosstalk, signal-integrity, and reliability risks and work with power-integrity teams to resolve them.

Requirements

Must-have technical skills and experience:

• 10+ years industry experience in ASIC/SoC physical design with hands-on clock implementation and timing-closure experience.
• Proven experience driving designs through physical-design convergence and successful tapeout.
• Deep expertise in clock distribution methodologies: H-trees, clock mesh, clock spines, hierarchical distribution, and clock gating/low-power techniques.
• Hands-on SPICE simulation and the ability to analyze transistor-level clock circuits and waveforms.
• Strong practical knowledge of timing concepts: skew, insertion delay, jitter, duty-cycle distortion, PVT variation, and multi-mode/multi-corner analysis.
• Experience with industry-standard implementation and signoff tools (Synopsys Fusion Compiler/ICC2 and/or Cadence Innovus; Synopsys PrimeTime; RC extraction and SI analysis tools).
• Familiarity with physical verification and DRC/LVS signoff flows and advanced-node effects on clock distribution.
• Proficiency in scripting/automation: TCL, Python, Perl, and Linux/Unix environments.

Nice-to-have:

• Experience developing custom clock methodologies for high-frequency designs and with advanced technology nodes.
• Knowledge of PLL behavior, clock-source modeling, PrimeClock or Infinisim, and correlating SPICE/STA/extraction results.
• Experience addressing IR-drop, EM, crosstalk, and SI issues specific to clock networks.
• Strong analytical and influencing skills to drive methodology changes across PD, timing, and CAD teams.

Education Requirements

Bachelor's, Master's, or PhD in Science or Engineering (examples: Electrical Engineering, Computer Engineering, related technical fields). The posting specifies degree-plus-experience combinations (BSc +6 years, MSc +5 years, PhD +4 years) and also expects substantial industry experience (the role cites ~10+ years in ASIC/SoC physical design).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.