Physical Design Engineer, Staff

Job Title

Physical Design Engineer, Staff

Role Summary

As a Staff Physical Design Engineer on the ASIC engineering team, you will own block- and subsystem-level physical implementation on advanced process nodes. The role focuses on timing closure, physical sign-off, backend flow development, and introducing AI-assisted automation into design flows.

Experience Level

Senior - typically 3–8 years of relevant digital physical-design experience. See Education Requirements for minimum experience tied to degree level.

Responsibilities

Primary responsibilities include:

• Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks and subsystems.
• Drive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementation.
• Perform signal integrity, power integrity, IR drop, and electromigration analysis using tools such as RedHawk/Voltus.
• Run full signoff verification flows (DRC, LVS, DFM, EM/IR) and resolve physical verification issues.
• Develop and maintain backend physical-design flows and automation using Python and TCL.
• Integrate AI-assisted tools for constraint optimization, timing-ECO suggestions, and violation triage.
• Optimize power and area via Multi-Vt strategies, clock gating, and power-aware synthesis.
• Collaborate with front-end, DFT, verification, and process teams to resolve design and manufacturability issues.

Requirements

Core technical skills and experience required for successful performance in this role.

Must-have:

• Strong experience with digital physical-design (backend) methodologies and timing closure workflows.
• Experience with advanced process nodes (e.g., TSMC N5, N4P, N3 or equivalent FinFET processes).
• Proficiency with EDA tools such as Synopsys ICC2, Cadence Innovus, Mentor Calibre, PrimeTime, and RedHawk/Voltus.
• Solid scripting skills in Python and TCL and experience building reusable automation and regression frameworks.
• Practical knowledge of STA, PnR, CTS, IR/EM analysis, and physical verification flows.
• Hands-on flow development experience: creating run environments, scripts, and automation for PnR, STA, and verification.

Nice-to-have:

• Exposure to or interest in Agentic AI-driven EDA methodologies and AI-assisted automation.
• Familiarity with DFT concepts (scan insertion, ATPG, BIST).

Education Requirements

Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design/verification/integration experience; OR Master's degree in Science, Engineering, or related field with 3+ years; OR PhD in Science, Engineering, or related field with 2+ years. Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.