Physical Design Engineer (Silicon Engineering)

Job Title

Physical Design Engineer (Silicon Engineering)

Role Summary

Implement and optimize ASIC physical design (RTL-to-GDSII) for Starlink hardware, collaborating with architecture, RTL, firmware, validation, and product teams. Deliver timing-, power-, and area-optimized, signoff-ready designs for space and ground systems.

Experience Level

Entry-level. The role requires at least 1 year of professional experience in RTL-to-GDSII physical design or physical design flow development.

Responsibilities

Primary responsibilities include full-chip physical implementation, signoff closure, and methodology development.

• Perform partition synthesis and full physical implementation steps: synthesis, floorplanning, power/ground grid generation, place-and-route, timing closure, noise analysis, physical verification, electromigration and IR drop checks, and logic equivalency.
• Develop and improve physical design methodologies, automation, and scripts for implementation steps.
• Collaborate with ASIC architects and RTL designers to set timing, power, and area targets and evaluate RTL/design tradeoffs.
• Identify and resolve design, timing, and congestion issues; propose and drive implementation of solutions.
• Run, debug, and fix signoff closure issues across STA, noise, equivalency, and physical verification flows.

Requirements

Key qualifications and skills. Education requirements are listed separately below.

• Must-have: Minimum 1+ years professional experience in RTL-to-GDSII physical design or physical design flow development.
• Must-have: Practical experience with implementation steps and signoff flows (timing closure, physical verification, EM/IR).
• Must-have: Proficiency with scripting and automation (examples: Python, TCL, Perl, shell, Makefile).
• Must-have: Ability to work extended hours and weekends as needed to meet critical milestones.
• Must-have: Compliance with U.S. export control (ITAR) requirements: applicants must be U.S. persons or otherwise eligible for required Department of State authorizations.
• Nice-to-have: Experience with industry-standard EDA tools and understanding of their algorithms and capabilities.
• Nice-to-have: Knowledge of deep sub-micron FinFET/CMOS physics, CMOS digital and analog design principles, and power dissipation characteristics.
• Nice-to-have: Familiarity with DFT/scan/MBIST/LBIST and their impact on physical design flows.
• Nice-to-have: Self-driven attitude and ability to work in a fast-paced, cross-disciplinary environment.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science is specified in the basic qualifications. The posting also requires at least 1+ years of professional experience in RTL-to-GDSII physical design or physical design flow development.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.