Physical Design Engineer, Senior Staff - Hod Hasharon
QualcommJob Title
Physical Design Engineer, Senior Staff - Hod Hasharon
Role Summary
Senior staff physical design engineer responsible for defining and owning full-chip and multi-die physical implementation methodology on advanced TSMC FinFET nodes. The role leads backend design strategy, develops scalable PD flow infrastructure, and mentors engineering teams while collaborating with foundry and EDA vendors.
Experience Level
Senior-level. Typical candidates have 10+ years of experience in digital physical design; minimum qualifications list degree-dependent experience thresholds (see Education Requirements).
Responsibilities
Lead technical execution and methodology for full-chip physical design and flow development.
- Architect and own full-chip PD strategy: floorplanning, PDN, clock architecture, placement & routing, and timing closure.
- Define and drive backend methodology standards for advanced-node tapeouts (N5/N4P/N3).
- Lead timing closure using MCMM, OCV, advanced ECO strategies and cross-corner sign-off.
- Oversee signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs.
- Design and implement scalable PD flow infrastructure and automation using Python and TCL (regressions, sign-off reporting, run management).
- Champion integration of Agentic AI in the PD flow: define use cases, evaluate tools, and prototype autonomous agents for floorplan exploration, timing closure, and ECO automation.
- Lead cross-functional design reviews and interface with foundry, EDA vendors, and internal research teams.
- Mentor and provide technical guidance to junior and mid-level PD engineers.
Requirements
Core technical skills and proven experience required for the role.
Must-have:
- 10+ years of experience in digital physical design with tapeouts on FinFET nodes (N7 and below).
- Deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off.
- Expert proficiency with EDA tools such as Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk/Voltus, StarRC/Quantus.
- Advanced Python and TCL scripting skills for large-scale PD automation and flow infrastructure.
- Proven experience designing, implementing, and owning end-to-end backend design flows at a team or organizational level.
- Demonstrated experience or clear vision for applying Agentic AI / autonomous agents to EDA challenges.
- Strong communication skills for presenting methodology decisions and tapeout readiness to senior management.
- Experience with power optimization techniques (DVFS, multi-Vt, power domains, UPF/CPF).
Nice-to-have:
- Experience with chiplets, 2.5D/3D IC physical design or advanced packaging technologies.
- Familiarity with AI/ML-driven EDA tool evaluation and vendor collaboration.
- Prior experience in tech lead, staff engineering, or similar leadership roles.
Education Requirements
Bachelor's degree in Science, Engineering, or related field with 6+ years relevant experience; OR Master's degree in Science, Engineering, or related field with 5+ years; OR PhD in Science, Engineering, or related field with 4+ years. Equivalent practical experience will be considered.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
