Physical Design Engineer / Senior Engineer

Job Title

Physical Design Engineer / Senior Engineer

Role Summary

Implement and optimize physical design (place-and-route) for complex ASICs and SoCs, focusing on performance, power, and timing closure. Work within the SoC and ASIC design organization on projects spanning high-performance computing and next-generation semiconductor products.

Collaborate with architecture, RTL, verification, DFT, and methodology teams to drive designs from synthesized netlist to sign-off and tape-out. Contribute to automation and low-power implementation methodologies.

Experience Level

Senior-level. The posting requests at least 2+ years of relevant industry or academic/project experience.

Responsibilities

Responsible for full physical design implementation and sign-off activities.

• Execute the full physical design flow from synthesized netlist to tape-out.
• Floorplanning, partitioning, and power planning including IR-drop analysis.
• Placement, clock tree synthesis (CTS), routing, and timing optimization to achieve timing closure across multi-mode multi-corner (MMMC) scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk, and design-rule violations.
• Perform RC extraction, physical verification, and formal verification-related tasks.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Develop automation and productivity tools using scripting and software development techniques.
• Collaborate with cross-functional teams to ensure successful project execution and to develop customized place-and-route solutions.

Requirements

Must-have:

• Minimum 2+ years of hands-on physical design experience on ASIC or SoC projects.
• Proven experience with floorplanning, placement, CTS, routing, timing optimization, and timing closure across MMMC scenarios.
• Experience with power planning and IR-drop analysis, RC extraction, and physical verification flows.
• Ability to analyze and fix timing, signal integrity, and physical-design rule issues; implement ECOs toward sign-off.
• Scripting/automation experience to build productivity tools and flows.
• Ability to work cross-functionally with architecture, RTL, verification, DFT, and methodology teams.

Nice-to-have:

• Experience developing low-power implementation methodologies and customized place-and-route solutions.
• Prior involvement in high-performance computing or next-generation semiconductor design projects.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is expected. The posting also accepts equivalent practical experience in lieu of a degree; the role expects at least 2+ years of relevant industry or academic/project experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.