Physical Design Engineer - Senior
QualcommJob Title
Physical Design Engineer - Senior
Role Summary
Senior ASIC/physical design engineer responsible for defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) for high-performance, low-power products. Works within the ASICS Engineering group and collaborates with cross-functional teams (software, hardware, architecture) to deliver block- and chip-level implementations.
Experience Level
Senior — typically requires several years of ASIC/physical-design experience. Minimums listed by the employer start at 2+ years; 3+ years of ASIC design experience is preferred.
Responsibilities
Key duties include:
- Define and implement block/SoC architectures, circuit specifications, and logic designs from system requirements.
- Perform RTL-to-GDS design flow tasks, synthesis, place-and-route, timing and power analysis, and verification activities.
- Use EDA and custom-layout tools (examples: RTL flows, Virtuoso) to execute designs and enable implementation.
- Develop and apply design verification and validation methods for IP and SoC integration.
- Collaborate with cross-functional teams to drive implementation strategy and meet system requirements.
- Produce detailed technical documentation for EDA/IP/ASIC projects.
Requirements
Must-have technical skills and experience:
- Practical ASIC design, verification, validation, or integration experience (professional experience expected).
- Experience with architecture and physical-design tools and flows (synthesis, P&R, timing and power analysis).
- Familiarity with RTL-to-GDS flows and common EDA/custom layout tools (e.g., Virtuoso).
- Experience with scripting and programming for automation and tool integration.
- Knowledge of design verification methods and ability to apply them to block/SoC designs.
- Strong technical writing and verbal communication skills; able to produce documentation and coordinate across teams.
Nice-to-have:
- Experience with low-power design techniques and power optimization.
- Experience in circuit design/layout flow or advanced timing/power optimization.
Education Requirements
Minimum qualifications: Bachelor's degree in science, engineering, or a related field with 2+ years of ASIC-related experience; OR Master's degree in science/engineering or related field with 1+ year of ASIC-related experience; OR PhD in a relevant field. Preferred: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
