Physical Design Engineer (New College Grad)
BroadcomJob Title
Physical Design Engineer (New College Grad)
Role Summary
Entry-level physical design engineer on the ASIC Products Division (APD) Physical Design team in San Jose. Work with experienced engineers to implement block-level floorplans, place-and-route flows, clock tree synthesis, timing closure, and signoff for advanced custom ASICs.
This role provides hands-on experience with industry EDA tools and script-driven automation in support of high-performance networking, AI/ML accelerators, and cloud ASICs.
Experience Level
Entry-level / New college graduate. Suitable for recent graduates or engineers with limited industry experience (typical 0–2 years).
Responsibilities
Primary duties include executing block-level physical implementation tasks and supporting signoff-quality flows.
- Participate in block-level floorplanning and run placement and route (P&R) flows using industry-standard EDA tools.
- Perform static timing analysis (STA), debug timing paths, and implement ECOs for timing closure.
- Run physical verification checks (DRC, LVS, ERC, antenna) and resolve signoff violations.
- Analyze IR drop and electromigration (EM) to ensure power-grid integrity.
- Develop and maintain automation scripts (TCL, Python, Ruby, Bash) to improve flow efficiency.
- Collaborate with team members on design integration and signoff tasks for advanced process nodes.
Requirements
Minimum skills and experience required for successful performance in this role.
- Solid understanding of digital CMOS logic design, standard-cell libraries, and semiconductor fundamentals.
- Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
- Hands-on experience with EDA tools from academic projects, coursework, internships, or prior work (examples: Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, Siemens tools).
- Proficient scripting skills (TCL, Python, Ruby, or Bash) and ability to develop flow automation.
- Ability to run or interpret physical verification and power-integrity checks (DRC/LVS, IR drop, EM).
- Legal authorization to work in the United States is required.
Nice-to-have:
- Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
- Basic understanding of DFT, low-power intent (UPF/CPF), and FinFET technologies.
- Strong debugging, problem-solving, and analytical skills.
Education Requirements
Either a Bachelor's degree in Electrical Engineering or Computer Engineering (the posting notes Bachelor's + ~2 years experience as one path) or a Master's degree in Electrical Engineering or Computer Engineering (recent graduates within the past 12 months were targeted). Fields cited: Electrical Engineering, Computer Engineering. (This role is targeted at new college graduates.)
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
