Physical Design Engineer Intern

Job Title

Physical Design Engineer Intern

Role Summary

Internship on Marvell's Physical Design team working on ASIC/processor physical implementation and timing analysis for data center, AI, storage, and networking chips. The role contributes to synthesis, floorplanning, place-and-route, timing closure, and cross-functional debugging under mentor guidance.

Experience Level

Entry-level (Internship). Targeted at students currently enrolled in a graduate program; specific posting requests candidates with expected graduation between Fall 2027 and Summer 2028.

Responsibilities

Work on implementation and timing tasks for complex logic blocks and support design convergence.

• Perform synthesis, floorplanning, placement & routing, clock insertion, timing analysis, and timing closure using industry EDA tools.
• Run static timing analysis and help resolve timing and congestion issues to meet performance, power, and area targets.
• Write and maintain scripts in Python, TCL, Perl, and Shell to automate flows and debug issues.
• Use CAD/EDA tools (e.g., Synopsys PrimeTime, Cadence Tempus, Mentor tools) to analyze and fix design violations.
• Collaborate with RTL, synthesis, and other design teams to integrate blocks and resolve cross-domain problems.
• Analyze failures, propose fixes, and iterate toward timing closure under direction of senior engineers.

Requirements

Key technical skills and eligibility for the internship.

• Must-have: Proficiency in scripting/programming (Python, TCL, Perl, Shell) and experience in a Unix environment.
• Must-have: Experience or familiarity with industry EDA tools such as Synopsys PrimeTime, Cadence Tempus, and Mentor tools.
• Must-have: Strong analytical, problem solving, and communication skills.
• Nice-to-have: Hands-on exposure to synthesis, place & route, clocking strategies, and timing closure workflows.
• Nice-to-have: Knowledge of RTL synthesis and Verilog/SystemVerilog.
• May require eligibility to access export-controlled technology; non-U.S. applicants may be subject to export license review.

Education Requirements

Currently enrolled in a Master’s degree program in Electrical Engineering, Computer Engineering, or a related technical field with expected graduation between Fall 2027 and Summer 2028. Relevant coursework includes VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog/SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics. (PhD candidates noted for potential additional intern compensation.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.