Physical Design Engineer II

Job Title

Physical Design Engineer II

Role Summary

Execute physical implementation tasks (synthesis, place-and-route, STA) for assigned ASIC/SoC partitions and own closure and signoff for those blocks. Collaborate with architects, RTL designers, DFT teams, and EDA vendors to identify and resolve implementation, signoff, and flow issues.

This is a fully on-site role based in San Jose, CA, working within eInfochips/Arrow engineering services teams to meet tight schedules and design goals.

Experience Level

Senior — requires 7+ years of hands-on physical design and implementation experience.

Responsibilities

Primary responsibilities include delivery, signoff, and process improvement for physical design partitions.

• Execute synthesis, place-and-route (PnR), and static timing analysis (STA) for assigned partitions to achieve timing, area, and power targets.
• Drive closure activities: timing convergence, EM/IR analysis, LEC, and physical verification signoff in coordination with methodology owners.
• Work cross-functionally with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
• Identify and mitigate physical design challenges early to enable efficient iteration and convergence.
• Refine and contribute to implementation and physical design methodologies (synthesis, PnR, EMIR, PDN, LEC).
• Troubleshoot EDA flow issues and collaborate with EDA vendors to resolve problems.
• Meet strict schedules and deliverables for assigned blocks.
• Work fully on-site in San Jose, CA and travel to client offices as requested by client leadership.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 7+ years of hands-on physical design and implementation experience, including synthesis, PnR, timing convergence, and physical verification.
• Must-have: Proficiency with EDA tools used for implementation and signoff (examples: Innovus, Tempus, Quantus) and familiarity with Cadence/Synopsys toolchains.
• Must-have: Strong understanding of physical design flows, STA, signoff flows, and ability to achieve timing and power targets.
• Must-have: Ability to collaborate effectively across RTL, architecture, DFT, and methodology teams.
• Nice-to-have: Experience with System-on-Chip (SoC) design and sub-7nm node technologies.
• Nice-to-have: Proven low-power design techniques and experience meeting tight schedules on complex designs.
• Nice-to-have: Strong TCL scripting skills to develop custom flows and methodologies on standard EDA tools.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: eInfochips

Headquarters: Bengaluru, India

eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.