Physical Design Engineer - Full Chip Implementation

Job Title

Physical Design Engineer - Full Chip Implementation

Role Summary

As a top-level physical design engineer you will own full-chip implementation from synthesis through GDSII, including floorplanning, placement and routing, clocking, timing closure, physical verification, and tapeout signoff. You will collaborate closely with RTL designers to drive PPA optimization and ensure timely signoff for inference-focused ASICs.

Experience Level

Senior — 10+ years of relevant chip planning and top-level physical design experience.

Responsibilities

Lead top-level PD activities and deliver tapeout-ready full-chip implementations.

• Define and implement full-chip floorplan and clocking across all PVT corners and modes.
• Manage multi-mode multi-corner (MMMC) timing closure at the top level.
• Establish and maintain timing constraints and hierarchical timing budgets between top level and blocks.
• Drive functional and timing ECOs and achieve final timing signoff for tapeout.
• Own end-to-end physical verification closure (DRC, LVS, ERC, antenna, density, fill) at block, subsystem, and full-chip levels.
• Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool/setup issues; perform layout fixes in Innovus as required.
• Build and maintain a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and signoff reviews.
• Collaborate with RTL and design teams to provide actionable feedback and accelerate iteration cycles.

Requirements

Must-have technical skills and hands-on tooling experience.

• 10+ years of experience in chip planning and top-level / full-chip physical design.
• Experience achieving top-level/full-chip closure on advanced nodes (5nm and below).
• Familiarity with RTL-to-GDSII flows such as Cadence (Innovus, Genus) or Synopsys (Fusion Compiler).
• Timing signoff experience with Synopsys PrimeTime or Cadence Tempus.
• Physical verification signoff experience with Pegasus or Calibre.
• Proven experience with hierarchical timing budgeting, constraint management, and ECO closure.
• Hands-on experience using Cadence Innovus for top-level assembly, routing, and layout fixes.

Nice-to-have:

• Familiarity with modern ML / LLM model architectures.
• Scripting experience (Python or similar) and use of AI-assisted programming tools.
• Startup experience or comfort working in fast-paced, cross-disciplinary teams.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.