Physical Design Engineer
QualcommJob Title
Physical Design Engineer
Role Summary
Join Qualcomm's SoC and ASIC physical design team to implement and deliver high-performance, low-power ASICs and SoCs across mobile, automotive, data center, and AI product lines. The role focuses on end-to-end physical design flow activities from synthesized netlist to tape-out.
This role works with architecture, RTL, verification, and methodology teams to achieve timing- and power-signoff on advanced process technologies and to develop automation and methodology improvements.
Experience Level
Mid-level - typically 2–10+ years of industry or relevant academic/project experience in physical design. Minimum experience requirement varies by degree (see Education Requirements).
Responsibilities
Execute and drive physical implementation tasks and collaborate with cross-functional teams to achieve tape-out and sign-off.
- Drive all stages of physical design from synthesized netlist to tape-out, including ECOs and sign-off support.
- Floorplanning, partitioning, power planning, IR-drop analysis, and placement strategy.
- Perform placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across MMMC scenarios.
- Perform timing analysis, RC extraction, physical verification, and resolve timing and signal-integrity issues.
- Analyze and mitigate crosstalk, noise, and signal-integrity concerns affecting timing and sign-off.
- Develop automation and productivity tools and scripts to improve design turnaround and repeatability.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure design convergence.
Requirements
Core skills and experience required for successful performance in this role. Degrees and degree-specific minimum experience are summarized separately under Education Requirements.
Must-have:- Practical experience in ASIC/SoC physical design and implementation (place-and-route, timing closure).
- Experience with timing analysis and closure across Multi-Mode, Multi-Corner (MMMC) flows.
- Hands-on experience with placement, CTS, routing, and timing optimization to achieve sign-off.
- Scripting and automation skills (Python, Tcl, Perl, Shell or similar) and comfort in Linux/Unix environments.
- Strong problem-solving skills and experience debugging ASIC implementation issues.
- Experience with Cadence Innovus, Synopsys Fusion Compiler (place-and-route), and Synopsys PrimeTime SI (static timing analysis).
- Familiarity with physical verification, formal verification tools, DFT-aware physical implementation, and low-power design methodologies.
- Experience with power-domain implementation, IR-drop and noise analysis, signal integrity sign-off flows.
- Proficiency in C/C++ for tooling or internal EDA integrations.
Education Requirements
Required: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is stated. Minimum qualifications specify degree-plus-experience options: Bachelor's +4 years, Master's +3 years, or PhD +2 years of relevant ASIC design/verification/validation/integration experience. The posting also allows relevant academic or project experience as part of the experience qualification.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
