Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Join Qualcomm's SoC and ASIC physical design team to implement and deliver complex, high-performance semiconductor designs. The role covers the full physical design flow for ASICs/SoCs across domains such as mobile, AI, data center, automotive, and high-performance computing.

Work with architecture, RTL, verification, DFT, and methodology teams to achieve timing, power, and sign-off goals on advanced process technologies.

Experience Level

Senior - role expects experienced engineers. The posting lists 10+ years of relevant industry experience as a general guideline.

Responsibilities

Drive physical implementation from synthesized netlist through sign-off, and develop automation and methodologies to improve quality and productivity.

• Execute full physical design flow: floorplan, placement, CTS, routing, and timing closure to tape-out.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Optimize timing across Multi-Mode Multi-Corner (MMMC) scenarios; analyze and resolve timing violations.
• Address signal integrity, crosstalk, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification support for sign-off.
• Implement engineering change orders (ECOs) and support design convergence.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams throughout project lifecycle.
• Contribute to low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting and software development techniques.

Requirements

Key must-have skills and experience for successful candidates, plus preferred skills.

Must-have

• 10+ years of industry experience in physical design (ASIC/SoC) or equivalent demonstrated project experience.
• Proven experience executing placement, CTS, routing, timing optimization, and timing closure (MMMC).
• Experience with floorplanning, power planning, IR-drop analysis, and ECO implementation.
• Strong problem-solving skills and experience debugging ASIC development issues.
• Experience developing automation, scripts, or tools (Python, Perl, TCL, Shell, C/C++ on Linux/Unix).
• Ability to collaborate across architecture, RTL, verification, and methodology teams to meet project goals.

Nice-to-have / Preferred

• Experience with Cadence Innovus and/or Synopsys Fusion Compiler for place-and-route.
• Static timing analysis using Synopsys PrimeTime SI and MMMC sign-off flows.
• Experience with physical verification, formal verification techniques, and sign-off methodologies.
• Low-power implementation techniques, power-domain implementation, and DFT-aware physical implementation.
• Signal integrity and noise analysis experience.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Science, Engineering, or a related technical field. The posting provides degree-based minimums: Bachelor's +6 years, Master's +5 years, or PhD +4 years of ASIC design/verification/validation/integration experience. The listing also cites 10+ years of industry experience as a general requirement in other sections and accepts relevant academic or project experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.