Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Experienced physical design engineer responsible for RTL-to-GDSII implementation and signoff for SoC/ASIC projects. Work on floorplanning, placement, CTS, routing, timing closure and physical verification for advanced technology nodes.

Collaborate with RTL, DFT, STA and backend teams to drive design convergence and tapeout readiness. Role is onsite in Santa Clara with a full-time, long-term assignment.

Experience Level

Mid-level — expects approximately 5–15 years of relevant physical design experience.

Responsibilities

Primary duties focus on physical implementation, timing closure and design signoff for complex SoCs and ASICs.

• Execute full-chip and block-level physical design from netlist to GDSII.
• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Perform timing closure, congestion analysis, and power optimization; resolve setup/hold violations and signal integrity issues.
• Support low-power implementation techniques and ECO flows.
• Drive design closure for advanced process nodes (7nm/5nm/3nm) and prepare designs for tapeout.
• Collaborate with RTL, DFT, STA, PD and backend teams to ensure convergence and signoff readiness.

Requirements

Technical skills and practical experience required to perform the role.

• Must-have: Strong hands-on experience with physical design flow from netlist to GDSII, including floorplanning, placement, CTS, routing and timing closure.
• Must-have: Hands-on experience with tools such as Cadence Innovus, ICC2, Synopsys PrimeTime/Tempus, and Mentor Calibre (or equivalent).
• Must-have: Knowledge of static timing analysis (STA), IR drop and EM analysis, DRC/LVS verification techniques.
• Must-have: Strong scripting skills (Tcl, Perl, Python) and proven debugging/problem-solving abilities.
• Nice-to-have: Experience with low-power methodologies, UPF/CPF flows, prior tapeout on complex SoCs or high-speed designs.
• Nice-to-have: Prior work on advanced technology nodes (7nm/5nm/3nm) and experience driving closure at those nodes.
• Work authorization: employer indicated openness to all visa types.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.