Physical Design Engineer

Role Summary

This role involves joining the Analog Backend team to work on digital island implementation within analog chips. The ideal candidate will tackle complex physical design challenges in mixed-signal environments.

Experience Level

Mid-level

Responsibilities

Key responsibilities include:

• Implementing ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification.
• Optimizing designs for performance, reliability, and manufacturability.
• Conducting chip-level power integrity analysis across multiple voltage domains.
• Collaborating with global cross-functional teams, including analog designers and verification engineers.

Requirements

Must-have qualifications:

• Experience in ASIC Physical Design.
• Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks.
• Knowledge of power integrity analysis (IR drop and electromigration).
• A team player who thrives in an international, collaborative environment.

Nice-to-have: Analog Layout experience.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.