Physical Design Engineer (Bengaluru)
CerebrasJob Title
Physical Design Engineer (Bengaluru)
Role Summary
As a member of the Physical Design team, you will perform block and full‑chip physical design and integration for wafer‑scale AI chips. The role covers synthesis, place‑and‑route, timing closure, physical verification, IR/EM analysis, and coordinating full‑chip sign‑off with RTL teams.
This position supports delivery of timing‑closed, verification‑clean blocks and integration work required to scale Cerebras' wafer‑scale architecture.
Experience Level
Senior — 7+ years of physical design or verification experience.
Responsibilities
Primary responsibilities include block‑level and full‑chip physical design, verification, and integration.
- Perform synthesis, place‑and‑route, timing closure, and block sign‑off.
- Lead block physical verification (PDV) and resolve full‑chip DRC and LVS issues.
- Perform IR/EM analysis and implement corrective actions.
- Contribute to full‑chip floorplanning and integration for wafer‑scale designs.
- Collaborate with RTL teams to optimize designs for power, performance, and area.
- Develop and maintain flow automation and scripts (Tcl, Python) to improve productivity.
- Provide technical leadership on block implementation and support transition to full‑chip integration.
Requirements
Must‑have technical skills and experience.
- 7+ years of physical design/verification experience.
- Proven experience in block/subsystem timing closure and STA.
- Strong knowledge of block‑level and full‑chip physical verification methodology (PDV).
- Expertise resolving block and full‑chip DRC and LVS issues using tools such as ICV or Calibre.
- Experience with IR/EM analysis and resolution.
- Experience with block physical design and full‑chip integration, including floorplanning.
- Proficiency in scripting (Tcl, Python) and making flow enhancements.
- Ability to work with RTL teams to optimize for physical design constraints.
- Capacity to take on a leadership role during wafer‑scale design ramp‑up.
Nice‑to‑have:
- Familiarity with the Synopsys tool suite.
- Experience across complete physical design flow, including synthesis and STA.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering preferred; Ph.D. in Electrical Engineering is also preferred (BSEE, MSEE, Ph.D. EE preferred).
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
