Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Responsible for physical implementation and signoff of custom IP and SoC designs from RTL to GDS, ensuring manufacturability and meeting timing, power, and area targets. Works within the physical design/ASIC team to perform implementation, verification, optimization, and contribute to methodology and flow automation. This role is based in Hyderabad (Madhapur); the employee must relocate to the location at their own expense.

Experience Level

Mid-level. Years of experience not specified in the posting.

Responsibilities

Key responsibilities include implementation, verification, analysis, and optimization across the full physical design flow.

• Implement designs from RTL to GDS including synthesis, floorplanning, placement, routing, and clock tree synthesis.
• Perform static timing analysis, timing closure, and timing signoff.
• Design and analyze power and clock distribution, multi-power-domain interactions, and power/noise behavior.
• Execute verification and signoff activities: formal equivalence checking, layout verification (LVS/DRC), electrical rule checks, reliability verification, and power-integrity analysis (static and dynamic).
• Analyze tool results, diagnose violations, and recommend fixes for current and future architectures.
• Optimize designs for power, frequency, and area; apply DFT where applicable.
• Contribute to development and automation of physical design methodologies and flows.

Requirements

Must-have technical skills and experience expected for the role. The posting does not list specific years or formal qualifications.

• Must-have: Hands-on experience with physical design implementation (synthesis, place-and-route, CTS), static timing analysis, and signoff flows using industry-standard EDA tools.
• Experience with power/clock distribution, timing closure, and multi-power-domain analysis.
• Experience with verification and signoff tools and flows: formal equivalence, LVS/DRC/ERC, layout verification, and power-integrity analysis.
• Familiarity with DFT and synthesis flows.
• Ability to analyze results and recommend design or flow changes to meet timing, power, and area targets.
• Nice-to-have: Experience automating physical design flows and developing methodologies.

Education Requirements

Not specified.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.