Physical Design Engineer
CerebrasJob Title
Physical Design Engineer
Role Summary
Member of the physical design team responsible for designing and analyzing 2.5D/3D integrated ASIC products. The role covers block-level and full-chip physical design, packaging, power, clock and cooling analysis, and resolving DRC/LVS/IR/EM issues.
Work closely with architecture and RTL teams to research and implement novel 3D integration concepts and optimize power, performance, and area.
Experience Level
Senior — 10+ years of physical design and verification experience.
Responsibilities
The primary responsibilities include design, verification, and integration of 3D/2.5D ASIC products and supporting physical implementation flows.
- Perform block and full-chip physical design and verification for 3D integrated products.
- Resolve DRC, LVS, PDV, IR, and EM issues using ICV/Calibre and similar tools.
- Optimize designs for power, performance, and area; collaborate on synthesis and timing closure.
- Develop and maintain scripts and flow enhancements (Tcl, Python) to improve productivity.
- Collaborate with RTL and architecture teams to influence microarchitecture for physical implementation.
- Conduct packaging, clock distribution, power delivery, and cooling analysis for multi-die integration.
- Lead full-chip floorplanning and integration efforts; support STA as needed.
- Take ownership of assigned design blocks and drive issues to closure.
Requirements
Core qualifications and skills required to perform the role.
- 10+ years of physical design/verification experience.
- Strong knowledge of block-level and full-chip physical verification methodology.
- Experience with block physical design, synthesis, PDV, IR, and full physical design flow.
- Expertise with ICV or Calibre for DRC/LVS resolution.
- Expertise in IR/EM analysis and resolution.
- Proficient with scripting (Tcl, Python) and improving flows.
- Proven ability to work with RTL teams to optimize for physical implementation and timing.
- Knowledge of 2.5D or 3D packaging solutions.
Nice-to-have:
- Experience with full-chip floorplanning and integration.
- Knowledge of clock distribution and cooling analysis.
- Experience with static timing analysis (STA).
- Familiarity with Synopsys tool suite.
Education Requirements
Not specified.
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
