Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Lead top-level signoff activities for complex SoCs on advanced process nodes (5nm / 3nm / 2nm). Drive full-chip timing, power integrity, clocking, and tapeout closure while collaborating with RTL, STA, PD, packaging, and foundry teams.

Experience Level

Senior — 8+ years of experience in physical design or signoff, with multiple full-cycle tapeouts on advanced nodes.

Responsibilities

Owner for top-level signoff and tapeout readiness; develop methodologies and resolve full-chip issues. Must demonstrate deep expertise in at least one specialized track.

• Lead top-level signoff and independently deliver tapeout-ready silicon.
• Collaborate with RTL, Physical Design, STA, Power Integrity, packaging, and foundry teams to diagnose and resolve structural, timing, and power issues.
• Execute, analyze, and debug full-chip timing, power, reliability, and clocking challenges across PVT corners and modes.
• Develop and optimize signoff methodologies to reduce turn-around time and improve PPA.
• Identify and mitigate timing, power, reliability, and clocking risks at full-chip level.
• Specialized tracks (expertise in at least one):
  • Top-Level EMIR (Power Integrity): static & dynamic IR drop analysis, electromigration verification, PDN optimization. Tools: Ansys RedHawk-SC, Cadence Voltus.
  • Top-Level Timing & STA: own full-chip STA, manage MMMC timing closure and ECOs. Tools: Synopsys PrimeTime, Cadence Tempus.
  • Top-Level Clock Distribution: design/analyze clock architectures (H-tree, mesh, hybrid) and drive CTS for ultra-low skew. Tools: Cadence Innovus, Synopsys Fusion, SPICE.

Requirements

Must-have technical skills and experience; preferred items noted.

• 8+ years in physical design/signoff with experience leading signoff-to-tapeout closure.
• Proven track record with multiple (2–3) successful tapeouts on advanced nodes (5nm, 3nm, 2nm).
• Deep knowledge of OCV, AOCV/POCV, and statistical timing methodologies.
• Strong scripting skills: Tcl, Python, Perl.
• Excellent debugging, analytical, and communication skills.
• Familiarity with relevant tools: Synopsys PrimeTime, Cadence Tempus, Cadence Innovus, Synopsys Fusion, Ansys RedHawk-SC, Cadence Voltus, SPICE.
• Preferred: experience with 2.5D/3D packaging signoff, foundry signoff flows (TSMC, Samsung, Intel), or background in HPC/AI accelerators and large-scale SoC designs.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Sintegra

Headquarters: Alameda, CA, United States

Sintegra is a semiconductor engineering firm that provides physical design and signoff services for advanced-node SoCs, specializing in timing closure, power integrity, clock distribution, and tapeout readiness for high-performance and AI/HPC designs.