Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Join the Physical Design organization to implement custom IP and SoC designs from RTL through GDS. Support implementation, analysis, optimization, and signoff activities for next-generation FPGA products while collaborating with RTL, timing, DFT, verification, and CAD teams.

Experience Level

Entry-level — requires 1+ year of experience in physical design engineering or physical design flows.

Responsibilities

Primary responsibilities cover the full physical design flow, verification, and design optimization for FPGA products.

• Implement custom IP and SoC designs from RTL to GDS to produce a manufacturing-ready design database.
• Execute and support synthesis, place & route, clock tree synthesis, floorplanning, and static timing analysis.
• Perform power, clock distribution, reliability, and noise analysis; support power optimization activities.
• Support verification and signoff tasks including equivalence checks, STA, power integrity, and layout verification.
• Analyze design and verification results; identify and resolve violations with senior engineers.
• Troubleshoot timing, placement, routing, and verification issues and implement corrective actions.
• Participate in development and automation of physical design methodologies and flows.
• Collaborate with cross-functional teams (RTL, timing, DFT, verification, CAD) to meet implementation and delivery goals.

Requirements

Must-have technical skills and experience. Degree and formal academic items are summarized under Education Requirements.

• 1+ year of hands-on experience in physical design engineering or physical design flows.
• Experience with RTL-to-GDS physical design flows and hands-on physical implementation tasks.
• Practical experience with synthesis, floorplanning, placement, routing, clock tree synthesis, and static timing analysis.
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA, or equivalent).
• Exposure to physical verification activities (DRC, LVS, ERC) and power analysis (IR drop, EM, SI/PI).
• Exposure to DFT, scan implementation, or related design-for-test methodologies.
• Experience with scripting for automation (Python, Tcl, Perl, Shell).
• Knowledge of digital logic design, CMOS technology, semiconductor design methodologies, and VLSI fundamentals.
• Strong analytical and problem-solving skills and ability to work with senior engineers and cross-functional teams.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. Preferred: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting also references academic, internship, or co-op experience involving semiconductor physical design, ASIC/SoC implementation, VLSI, or related design flows.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.