Physical Design Engineer
Info-WaysJob Title
Physical Design Engineer
Role Summary
Perform full-chip and block-level physical design tasks including floorplanning, place-and-route (P&R), timing closure, power planning, clock tree synthesis (CTS), signal integrity (SI) mitigation, physical verification (PV) and I/R drop analysis for complex top-level and block-level designs.
Work on physical design projects from netlist to GDS, coordinate STA and signoff flows, and support automation and verification efforts.
Experience Level
Mid-level. Specific years of experience not specified.
Responsibilities
Primary responsibilities include implementation, optimization and verification of physical design deliverables for SoC blocks and top-level integration.
- Create and execute floorplans for full-chip, macro and block-level designs, including macro placement and power grid implementation.
Requirements
Must-have technical skills and tools for immediate contribution; preferred items listed separately.
- Must-have: Proven experience handling complex top-level/multi-block designs: floorplanning, placement, CTS, routing and timing closure.
- Must-have: Ability to take hard macros through full P&R flow from netlist to GDS, including timing closure and physical verification.
- Tools: Experience with industry EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime SI/Tempus and Calibre.
- STA & Timing: Strong static timing analysis skills, ECO generation, corner/voltage handling and timing correlation.
- Power & Low-Power: Power grid design, power collapse/low-power techniques and knowledge of UPF/CPF flows.
- Physical Verification: Experience running DRC/LVS/ERC and implementing fixes using Calibre or equivalent.
- Automation: Scripting experience in Perl, Python or Shell is preferred for automation tasks.
Education Requirements
Not specified.
About the Company
Company: Info-Ways
IT staffing and consulting firm focused on recruiting and placing engineering and technology contractors and professionals.
