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Physical Design Engineer

Qualcomm
October 20, 2026
Full-time
On-site
Santa Clara, California, United States
$190,200 - $285,400 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Physical Design Engineer

Role Summary

Work on Physical Design for complex ASICs and SoCs, contributing to floorplanning, placement, CTS, routing, timing closure, low-power implementation, and sign-off. The role is on an engineering team delivering advanced semiconductor products across mobile, AI, automotive, and data center domains.

Experience Level

Senior-level role. Candidates should have substantial industry experience in Physical Design; the posting indicates 10+ years is preferred.

Responsibilities

Execute and lead physical implementation tasks and collaborate with cross-functional teams to bring designs to tape-out.

  • Drive full physical design flow from synthesized netlist to tape-out (floorplan, placement, CTS, routing, timing closure).
  • Perform partitioning, power planning, IR-drop and signal-integrity analysis, and MMMC timing closure.
  • Analyze and resolve timing violations, crosstalk, and physical DRC/LVS issues; perform RC extraction and physical verification.
  • Implement ECOs and support convergence to sign-off.
  • Collaborate with architecture, RTL, DFT, verification, and methodology teams to meet project goals.
  • Develop automation and productivity tools using scripting and software-development techniques.

Requirements

Core technical and practical skills required; preferred skills that improve fit are marked accordingly.

  • Must-have: 10+ years of industry experience in Physical Design (ASIC/SoC) and demonstrated delivery of complex designs.
  • Must-have: Hands-on experience executing physical design flow, timing optimization, and timing closure across Multi-Mode Multi-Corner scenarios.
  • Must-have: Strong problem solving and ASIC development/debugging skills; experience with scripting/automation (Python, Tcl, Perl, shell) and Linux/Unix environments.
  • Nice-to-have: Experience with place-and-route tools such as Cadence Innovus or Synopsys Fusion Compiler, and STA with Synopsys PrimeTime SI.
  • Nice-to-have: Knowledge of physical verification/sign-off methodologies, formal verification tools, low-power implementation techniques, CTS and routing optimization, signal-integrity/noise analysis, and DFT-aware physical implementation.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is listed. The posting also specifies minimum qualifications alternatives (Bachelor's +6 years, Master’s +5 years, or PhD +4 years) indicating advanced degrees or equivalent experience are acceptable.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-15