Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Implement physical design for ultra-high-performance, low-power data processing processors. Work within the physical design team to translate RTL into floorplans, placement, routing and timing-closed layouts that meet performance, power and area (PPA) targets.

Collaborate with RTL designers and global teams to define clocking, power-grid, and automation flows and deliver PD partitions on schedule.

Experience Level

Senior — more than 5 years of experience in high-performance semiconductor design.

Responsibilities

Primary responsibilities include:

• Implement physical design for ultra-high-performance, low-power data-processing chips.
• Collaborate with RTL designers to achieve PPA targets and recommend trade-offs.
• Floorplanning and exploring placement and routing techniques to improve PPA.
• Perform timing closure for very-high-frequency designs; perform hand placement of logic when needed.
• Define low-latency/low-skew clock tree methodology and clock network design.
• Define power-grid structures and ensure EM/IR compliance.
• Develop scripts and automation to improve turn-around and regression flows.

Requirements

Must-have:

• More than 5 years' experience in high-performance semiconductor/ASIC physical design.
• Practical knowledge of Verilog and the full ASIC design flow.
• Expertise in logic synthesis, prototyping, timing analysis and floor-planning.
• Experience automating flows (Perl, Tcl, Python) and understanding of full PD methodology.
• Experience with Cadence Innovus on 7nm or smaller process nodes.
• Strong communication skills and ability to work with a distributed/global team.
• Proven track record of meeting project milestones and mentoring junior engineers.

Nice-to-have:

• Background in computer architecture.
• Familiarity with synthesizable RTL constructs (flops, FIFOs, clock-domain crossing).
• Familiarity with high-speed protocols (PCIe, 100G+ Ethernet) and DDR4.
• Ability to create regression scripts and run batch/grid jobs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Science (BS or MS in EE or CS).

About the Company

Company: Tachyum

Headquarters: Sunnyvale, CA, USA

Tachyum develops Prodigy, a universal processor that combines CPU, GPU, and TPU capabilities to deliver high-performance, energy-efficient computing for AI, HPC, and cloud data centers. The company focuses on ultra-low power, hyperscale deployments and operates offices in the United States and Slovakia.