Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Experienced physical design engineer responsible for leading Netlist-to-GDSII physical implementation of high-performance, low-power SoCs at advanced process nodes. The role works on floorplanning, placement, CTS, routing, timing closure and physical verification in collaboration with RTL, STA, DFT, CAD and verification teams.

Experience Level

Mid-level - preferred 5–10 years of relevant ASIC/SoC physical design experience.

Responsibilities

Deliver complete physical implementation from netlist to GDSII and drive closure on PPA and tapeout schedules.

• Execute Netlist-to-GDSII / RTL-to-GDSII physical design flow for block and SoC levels.
• Perform floorplanning, power planning, placement, CTS, routing and physical optimization.
• Drive timing closure; resolve setup/hold, congestion, DRC and routing issues.
• Analyze timing and physical reports and implement fixes and ECOs.
• Address advanced-node issues: IR drop, electromigration, crosstalk/signal integrity and design-rule constraints.
• Coordinate with RTL, STA, architecture, CAD, DFT and verification for signoff readiness.
• Support physical verification and final signoff activities toward tapeout.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• 5–10 years hands-on ASIC/SoC physical design experience, including Netlist-to-GDSII flow.
• Proven experience with Cadence Innovus.
• Strong knowledge of floorplanning, placement, CTS, routing, timing closure and PPA optimization.
• Experience with STA tools such as Synopsys PrimeTime.
• Experience with physical verification/signoff tools such as Calibre.
• Familiarity with Synopsys Fusion Compiler.
• Practical experience resolving IR drop, EM, crosstalk and signal-integrity issues at block or SoC level.
• Experience working on high-performance SoC/GPU/ASIC designs and driving tapeout-quality implementations.

Preferred:

• Direct experience with TSMC 3nm or 2nm technologies.
• Experience with GPU, CPU, AI accelerator or HPC SoCs and aggressive PPA targets.
• Proven advanced-node tapeout and ECO experience.

Education Requirements

Not specified.

About the Company

Company: Metalight Solutions

Technology staffing and engineering services firm providing contract and contract-to-hire talent for semiconductor, hardware, and software roles, including physical design and ASIC engineering support.