Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Experienced physical design engineer working on RTL-to-GDSII implementation and signoff for advanced SoC/ASIC designs. The role focuses on floorplanning, placement, CTS, routing, timing closure, and tapeout readiness within a cross-functional semiconductor team.

Experience Level

Mid-level — 5–15 years of relevant physical design experience.

Responsibilities

Deliver end-to-end physical design tasks and collaborate with frontend and backend teams to achieve tapeout.

• Execute full-chip and block-level physical implementation from netlist to GDSII.
• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification tasks.
• Drive timing closure, congestion analysis, and power optimization.
• Analyze and resolve setup/hold violations, signal integrity, IR drop, and EM issues.
• Support low-power implementation techniques and ECO flows.
• Collaborate with RTL, DFT, STA, and PD teams for design convergence and tapeout readiness.

Requirements

Core technical skills and tools required; preferred items noted separately.

• Hands-on experience with physical design flow from netlist to GDSII.
• Proven expertise in floorplanning, placement, CTS, routing, and timing closure.
• Experience with industry tools such as Cadence Innovus, ICC2, PrimeTime, Tempus, and Calibre.
• Knowledge of static timing analysis (STA), DRC/LVS verification, IR drop and EM analysis.
• Strong scripting skills (Tcl, Perl, or Python) for automation and debugging.
• Excellent debugging and problem-solving skills for physical design issues.

Nice-to-have:

• Experience with advanced process nodes (7nm/5nm/3nm) and prior tapeout on complex SoCs.
• Familiarity with low-power methodologies and UPF/CPF flows.
• Strong communication and cross-team collaboration experience.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.