Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Perform full-chip physical implementation for ASIC/IC designs from RTL to tape-out, including synthesis, place-and-route, timing closure, and physical verification. Work within a chip implementation team and collaborate with RTL designers and verification engineers across multiple California sites (San Diego, San Jose, Irvine).

Experience Level

Senior — 12+ years of relevant physical design experience.

Responsibilities

Primary technical responsibilities include:

• Execute physical design flow: synthesis, placement, clock tree synthesis, routing and timing closure.
• Perform physical verification and signoff-quality static timing analysis (STA), EM/IR analysis, and timing closure strategies.
• Develop floorplans and handle top-level floorplanning tasks for complex designs.
• Design and optimize clocking (CTS), including custom clock trees, insertion reduction, and skew balancing.
• Support tape-out readiness and full RTL-to-tape-out flows.
• Contribute to flow and methodology development and automation.
• Collaborate with IC design (RTL) engineers to resolve implementation and timing issues.

Requirements

Must-have technical skills and experience:

• Hands-on experience across the full physical design cycle (RTL-to-tape-out).
• Proficiency with industry EDA tools for synthesis, P&R, STA, and physical verification.
• Strong scripting skills (TCL and/or Perl) for automation and flow development.
• Proven experience in timing closure methodologies and signoff practices.
• Clear verbal and written communication skills for cross-team coordination.

Nice-to-have:

• Deep experience with top-level STA, EM/IR signoff, and complex clock-tree architectures.
• Experience developing or improving physical design flows and automation frameworks.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering or Electronics Engineering.

About the Company

Company: Oso Semiconductor

Headquarters: Mountain View, CA, United States

Early-stage fabless semiconductor startup developing mmWave beamforming RFICs that deliver 2–4x power reduction for phased array systems across SATCOM, 5G, and radar. Founded by UC Berkeley PhDs, the company has raised Series A funding and works with defense and commercial customers on full-custom mmWave front-end and beamformer chips.