Physical Design Director

Job Title

Physical Design Director

Role Summary

Lead the Digital Business Unit's physical design efforts to deliver complex SoCs on advanced process nodes, owning end-to-end RTL-to-GDSII physical implementation to meet performance, power, area, timing, and manufacturability targets.

Manage and grow a physical design organization, provide technical leadership and mentoring, and coordinate with RTL, DFT, CAD, packaging, and system teams to ensure predictable tapeouts.

Experience Level

Senior; 15+ years of experience in physical design and proven track record of leadership and successful tapeouts of complex, high-performance SoCs on advanced nodes.

Responsibilities

Primary responsibilities include technical leadership, delivery ownership, and team development.

• Own end-to-end RTL-to-GDSII execution across SoC programs: synthesis, floorplanning, placement, CTS, routing, and signoff.
• Define and execute timing, power, and physical signoff strategies (STA, SI, IR/EM) to ensure first-pass silicon success.
• Drive PPA optimization at architecture and implementation levels through congestion management, routing methodologies, and library strategy.
• Establish and enforce DRC/LVS closure practices, lead physical verification, and streamline ECO flows for aggressive schedules.
• Partner with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals.
• Build and scale high-performing physical design teams; mentor senior engineers and technical leads.
• Define and deploy automated design methodologies using TCL, Python, Perl, and collaborate with CAD to improve flow efficiency and scalability.
• Manage risk, schedules, and cross-functional dependencies for high-complexity designs on advanced nodes (22nm, 16nm, 5nm, 3nm, etc.).
• Champion low-power design strategies (UPF/CPF) and enable power-efficient architectures.
• Travel as required (approximately 10%).

Requirements

Required technical skills and leadership qualities.

• 15+ years of physical design experience on advanced process nodes (including 28nm, 22nm, 16nm, 10nm, 5nm and below).
• Deep expertise in full-chip physical design: floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and signoff methodologies.
• Strong command of STA, constraint development, timing closure, signal integrity, and IR/EM analysis.
• Proven ability to define, drive, and scale design methodologies and flows to meet QoR (PPA) targets and delivery predictability.
• Solid understanding of device, interconnect, and circuit challenges in advanced/UDSM nodes and scaling complexities.
• Proficiency in scripting (TCL, Python, or similar) and experience driving automation with CAD teams.
• Strong cross-functional collaboration and executive-level communication and stakeholder management skills.

Education Requirements

B.Tech / M.Tech (or higher) in Electrical / Electronics Engineering or a related field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.