Physical Design - CAD Lead

Job Title

Physical Design 6 CAD Lead

Role Summary

Lead development of physical-design (PD) CAD flows and flow infrastructure for energy-efficient processor designs. Seed hire for a new hardware engineering group responsible for building end-to-end PD flows, automation, and tooling to enable predictable, repeatable tapeouts across multiple product lines.

Experience Level

Senior-level. Typical background: Master's degree with 5+ years' industry experience or PhD with 3+ years' industry experience in physical design/CAD.

Responsibilities

Owner for PD flows, infrastructure, automation, and regression to enable fast, high-quality hardware delivery.

• Design, develop and maintain PD flows and methodology for FinFET and multi-patterning technologies (Cadence Tempus or Synopsys Primetime).
• Create repeatable, process-agnostic PD flows and end-to-end build/signoff flows in collaboration with PD team leads.
• Develop flow infrastructure and orchestration to support multiple product lines under tight schedules.
• Build regression frameworks and quality checks to minimize flow-related rework for designers.
• Develop utilities for collateral quality checking and a unified environment for specifying collaterals and flow dependencies.
• Coordinate work with third-party vendors and integrate external resources into internal flows.
• Continuously improve flow consistency, efficiency, and automation.

Requirements

Core technical requirements and skills.

• Strong Python and scripting skills; proficient in TCL and shell scripting.
• Experience developing workflow orchestration or flow infrastructure (e.g., Airflow, flowtracer).
• Familiarity with Kubernetes and containerization for CAD environments.
• Experience implementing regression frameworks and CI for CAD flows.
• Database proficiency (SQL and/or document stores such as MongoDB).
• Intimate knowledge of hardware design workflows for Physical Design and RTL/DV.
• Experience working with and coordinating third-party vendors.

Nice-to-have:

• Experience with full-chip RTL/DV and PD flows, timing constraint definition, and signoff.
• Knowledge of circuit design, device physics, deep sub-micron and SOI technology implications for physical design.
• Experience integrating analog/mixed-signal macros and verifying IP collaterals.

Education Requirements

Masters degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.