Physical Design and Signoff, Sr. Principal AE

Job Title

Physical Design and Signoff, Sr. Principal AE

Role Summary

Senior Field Applications Engineer focused on digital implementation and signoff. You will work directly with customers and Cadence R&D to deploy and improve synthesis, place-and-route, and signoff flows that meet PPA and design-closure objectives.

Primary activities include customer engagements, technical evaluations and benchmarks, product feedback to R&D, and enabling adoption of Cadence backend EDA technologies.

Experience Level

Senior-level. Requires 10+ years of industry physical design experience with strong expertise in digital implementation and signoff.

Responsibilities

Key responsibilities include:

• Provide technical support to customers on backend digital implementation and signoff, including place & route, timing and power closure, and IR drop analysis.
• Advise customers on using Cadence tools and flows to meet project schedules and design goals.
• Lead technical evaluations, benchmarks, demonstrations, and presentations.
• Collaborate with R&D to drive tool and methodology improvements based on customer requirements.
• Develop and augment flows using scripting (Tcl/Perl/Python); capture and document best practices and lessons learned.
• Promote adoption of Cadence tools and mentor other engineers on successful flows and techniques.

Requirements

Must-have skills and experience:

• 10+ years of industry physical design experience.
• Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
• Experience with IC digital implementation flows and backend EDA tools: place & route, IR drop, timing and power closure.
• Experience with advanced process nodes (10nm and below).
• Proficiency in scripting languages such as Tcl, Perl, or Python.
• Strong customer-facing communication, problem-solving skills, and ability to drive technical engagements.

Nice-to-have:

• Experience with frontend flows and tools: synthesis, DFT, logical equivalence checking.
• Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, ICC/ICC2, DC, or PrimeTime.
• Experience with advanced nodes at 5nm and below.

Education Requirements

Minimum: BS in Computer Science, Computer Engineering, Electrical Engineering, or a related field. Preferred: MS in Computer Science/Engineering, Electrical Engineering, or a related field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.