Performance Modeling Engineer - Sr. Staff (Processor, AI Accelerator, SoC Architecture)
QualcommJob Title
Performance Modeling Engineer - Sr. Staff (Processor, AI Accelerator, SoC Architecture)
Role Summary
Senior engineer responsible for architectural exploration, system-level performance analysis, and optimization of processors, AI accelerators, and SoC platforms. The role partners with architecture, RTL, verification, software, and systems teams to build and validate high-fidelity performance models and to guide design tradeoffs from concept through silicon.
Experience Level
Senior - expects 10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.
Responsibilities
Primary responsibilities focus on developing performance models, running architectural studies, and providing actionable recommendations to engineering leadership.
- Develop and maintain transaction-level (TLM/SystemC) and analytical performance models for processors, accelerators, memory hierarchies, and interconnects.
- Create detailed models of cache hierarchies, coherent interconnects, memory subsystems, DMA engines, and shared-memory multiprocessor systems.
- Evaluate architectural tradeoffs for performance, power, area, latency, bandwidth, and scalability.
- Analyze workload behavior, identify system bottlenecks, and drive optimization through simulation and modeling.
- Perform deep analysis of branch prediction, hardware prefetching, speculative execution, load/store architectures, cache coherence protocols, and memory consistency models.
- Model and validate multithreaded/multiprocessor workload behavior and correlate models with RTL, emulation, and silicon results.
- Present architectural findings and recommendations to engineering leadership and cross-functional teams.
Requirements
Must-have technical skills and experience for successful execution of the role.
- 10+ years industry experience in computer architecture, microarchitecture, or performance modeling.
- Strong understanding of processor architecture, microarchitecture, cache and memory hierarchy design, and multicore/SMP systems.
- Experience developing transaction-level models (TLM/SystemC), analytical performance models, or architectural simulators.
- Deep knowledge of cache behavior (capacity/conflict effects, latency, prefetching, locality) and cache coherence interactions.
- Familiarity with modern coherence protocols (ARM CHI, ACE, MESI/MOESI) and memory consistency models, atomic operations, and synchronization semantics.
- Proficient software development skills in C++, Python, or equivalent languages for modeling and tooling.
- Ability to correlate pre-silicon models with silicon measurements and performance counters.
Nice-to-have:
- Experience modeling AI accelerators, GPUs, heterogeneous compute, NoC architectures, memory controllers, DDR/HBM, virtualization (SR-IOV), or power-performance analysis techniques.
- Familiarity with formal verification methods for cache coherence and memory ordering.
Education Requirements
Degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field is expected: options listed in the source include Bachelor's, Master's, or PhD. The posting documents degree-to-experience equivalencies (Bachelor's +6 years, Master's +5 years, PhD +4 years) and also states typical expectations of ~10+ years of industry experience. Equivalent practical experience is referenced by the degree/experience alternatives.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
