PDK Engineer Extraction Development

Job Title

PDK Engineer Extraction Development

Role Summary

Develop and validate Process Design Kit (PDK) collateral—extraction, LVS, physical verification decks, and device models—to enable silicon design flows for advanced process nodes. Work within the Design Technology Platform Enablement group and collaborate with design teams, EDA vendors, and process technology experts.

Experience Level

Senior-level. Posting specifies: Bachelor's +12 years, Master's +10 years, or Ph.D. +8 years of relevant PDK development and validation experience.

Responsibilities

Primary responsibilities include creating and validating PDK assets, enabling EDA tool flows, and driving automation and QA for scalable delivery.

• Develop and maintain PDK collateral: Metal R/C extraction runsets, LVS, physical verification decks, and transistor/device models.
• Validate PDK libraries for design-rule compliance and correct implementations for advanced process nodes.
• Create test structures and run simulations for physical verification, parasitic extraction, and device modeling.
• Debug PDK-related issues with root-cause analysis and error dispositioning.
• Develop QA methodologies and automation tools to improve coverage and scalability across technology nodes.
• Partner with EDA vendors to enable new tool functionality and improve design workflows.
• Document and deliver design flows, guidelines, and tutorials for internal design teams and external users.
• Engage with cross-functional teams to support new process development and ensure PDK usability.

Requirements

Must-have technical skills and experience:

• Hands-on experience with physical verification tools (Calibre, Pegasus, ICV) and parasitic extraction tools (StarRC, QRC).
• Proficiency in scripting for automation (Python, TCL, Perl).
• Experience with PDK enablement for advanced process nodes, including device modeling and layout verification methodologies.
• Experience building test structures and validating extraction and LVS flows.
• Strong debugging, root-cause analysis, and cross-team collaboration skills.
• Experience driving automation and QA for scalable PDK delivery.

Nice-to-have:

• Familiarity with reliability verification (EM/IR) and ESD concepts.
• Experience with 3DIC flow methodologies and low-power design techniques.
• Knowledge of CMOS device physics and process technology.
• Presentation and documentation skills for stakeholder communication.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (with ~12+ years experience), OR Master's degree (with ~10+ years experience), OR Ph.D. (with ~8+ years experience). The posting allows equivalent practical experience in lieu of a listed degree.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.