Package Layout Design Staff/Senior Staff Engineer
Marvell TechnologyJob Title
Package Layout Design Staff/Senior Staff Engineer
Role Summary
Join the Advanced Packaging team to design and deliver high-speed microelectronic packages from concept through tapeout. The role focuses on package layout, manufacturability, performance, reliability and cost compliance while working with package architects, ASIC teams, and external suppliers.
Experience Level
Senior - posting specifies 4+ years of related professional experience.
Responsibilities
The engineer will lead package layout and development activities across design, verification, and production phases. Key responsibilities include:
- Drive package development from concept through tapeout ensuring manufacturability and performance.
- Define and implement layout constraints for high-speed interfaces and power delivery.
- Collaborate with package architects, substrate suppliers, OSATs, and silicon fabs to execute designs.
- Optimize power plane design and translate system-level power delivery into package solutions.
- Support new product introduction (NPI) activities and coordinate cross-functional handoffs with ASIC physical design and validation teams.
- Contribute to tool, process, and flow development, including library maintenance and basic scripting for automation.
Requirements
Must-have technical skills and qualifications:
- 4+ years of related professional experience.
- Proficiency with IC package layout tools such as Cadence APD or Siemens (Mentor) Xpedition.
- Strong understanding of high-speed interface package requirements and constraint implementation.
- Experience collaborating with substrate suppliers, OSATs, and silicon fabrication partners.
- Expertise in power plane design and knowledge of substrate design rules.
- Familiarity with foundry design rules and substrate manufacturing constraints.
- Ability to work across global, cross-functional teams.
- Eligibility to access export-controlled technology; candidates may be subject to export license review.
Nice-to-have:
- Experience with NPI from concept through production.
- Experience optimizing die floorplan with ASIC physical design teams.
- Knowledge of 2D/2.5D and emerging packaging architectures (CoWoS, EMIB, CPO, CPC).
- High-level understanding of thermal and mechanical package constraints (warpage, TIM).
- Experience contributing to tool/process development and scripting for automation.
Education Requirements
Not specified.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
