Package Design Engineer

Job Title

Package Design Engineer

Role Summary

Work within the Qualcomm Data Center packaging engineering team to design, layout, verify, and tape out advanced IC packages and SiP modules for high-performance data center SoCs. The role focuses on optimizing mechanical, electrical, and thermal performance across chip, package, and board interfaces and improving package design flows and automation.

Experience Level

Mid-level — typically requires 3+ years of relevant industry experience; preferred candidates have 5+ years.

Responsibilities

Primary responsibilities include package architecture, physical design, verification, and multi-disciplinary optimization.

• Own advanced package selection, new-generation package structures, and configuration optimization.
• Perform package/SIP physical design, layout, optimization, design verification, and support tape-out activities.
• Collaborate with cross-functional teams to meet mechanical, electrical, and thermal targets for SoC packages.
• Implement package and module physical designs and define package pinout with system requirements in mind.
• Define and develop design verification and automation strategies to streamline package design and release flows.
• Drive methodology and tool/process improvements with internal teams and external vendors; resolve feature and defect issues.
• Explore and evaluate new CAD tools and verification flows; partner with product teams to optimize chip floorplan and bump placement.

Requirements

Must-have technical skills and tools, plus preferred additional capabilities.

• Must-have: Proficiency with Cadence APD/SiP and practical package design/layout experience.
• Knowledge of IC packaging structures and chip-package and package-board interactions.
• Familiarity with high-speed I/O interfaces and basic electromagnetic field concepts relevant to packaging and signal integrity.
• Experience ensuring package design meets SI/PI requirements and participates in package design reviews.
• Nice-to-have: Experience with Cadence Allegro platform (PCB Editor, APD/SiP) and advanced package configurations (flip-chip BGA, 2.5D/3D interposers).
• Familiarity with SI/PI and EM tools (examples: XtractIM, PowerSI, HFSS, Q3D), package model extraction, S-parameters, and RLGC modeling.
• Understanding of substrate manufacturing processes, structure, design rules, and material properties; awareness of typical packaging failure modes.
• Experience with Calibre, DRC/DFM practices, high-speed layout constraints (crosstalk mitigation, differential pairs), and thermal/material considerations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related technical field. The posting specifies experience expectations tied to qualifications: minimum ~3 years for basic qualification and commonly ~5+ years for preferred/senior experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.