NPU Synthesis Engineer, Principal

Job Title

NPU Synthesis Engineer, Principal

Role Summary

Drive RTL-to-GDS synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems used in AI/ML accelerators. Work closely with Architecture, RTL design, STA, DFT, and Physical Design teams to deliver high-quality, power-efficient silicon on advanced process nodes.

Experience Level

Senior-level (Principal). The posting provides experience bands: Senior Engineer (3–5 years), Lead (5–8), Staff (8–12), Sr Staff (12–18), Principal (18+).

Responsibilities

Primary responsibilities include synthesis, timing closure, and improving quality-of-results for complex hierarchical designs.

• Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
• Develop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.
• Drive pre-layout and post-layout timing closure across multiple modes and process corners.
• Optimize designs for PPA (Performance, Power, Area) using physical-aware synthesis methodologies.
• Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.
• Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.
• Perform quality checks and verification related to timing, low-power flows, and design rule convergence.
• Analyze and improve synthesis QoR through scripting and flow enhancements.
• Support tapeout activities and drive continuous improvements in synthesis methodologies.

Requirements

Must-have technical skills and hands-on experience.

• Strong understanding of the ASIC design flow from RTL to GDS and hands-on experience with RTL synthesis and timing closure.
• Experience developing and maintaining synthesis constraints and flows; strong timing analysis skills.
• Practical experience with Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
• Timing signoff experience using PrimeTime or equivalent tools.
• Experience with low-power design methodologies and UPF-based flows.
• Good understanding of clocking architecture, timing constraints, and timing signoff practices.
• Proficiency in TCL and scripting languages such as Python or Perl to automate flows and analyze QoR.
• Excellent debugging, problem-solving, and cross-functional collaboration skills.

Nice-to-have:

• Experience on AI/ML accelerators (NPU), DSP, GPU, or high-performance compute architectures.
• Experience with advanced process nodes (5nm, 4nm, 3nm and below) and physical-aware synthesis/hierarchical methodologies.
• Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
• Proven track record of successful SoC or IP tapeouts.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related engineering field. The posting specifies experience alternatives: Bachelor + ≥3 years hardware engineering experience; Master + ≥2 years; PhD + ≥1 year. Equivalent practical work experience is accepted as described in the posting.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.