NPU STA/Timing Engineer

Job Title

NPU STA/Timing Engineer

Role Summary

This role performs static timing analysis (STA) and drives timing convergence and signoff for NPU and SoC designs. The engineer works with backend implementation, process enablement, and cross-functional teams to validate timing across corners and optimize STA flows.

Experience Level

Mid-level. Typical hire has 2+ years of hardware/STA experience; stronger candidates often have 5–10 years of STA/timing experience.

Responsibilities

Key responsibilities include:

• Set up STA flows, perform convergence activities, and drive timing signoff for multi-mode, multi-voltage-domain designs.
• Perform timing analysis, validation, and debug across multiple PVT corners using PrimeTime and/or Tempus.
• Run and optimize STA flows; perform Spice-to-STA correlation and flow optimization.
• Evaluate timing methodologies and tools across designs and technology nodes.
• Develop automation scripts within STA/PD tools to improve methodology and efficiency.
• Collaborate with cross-functional teams and produce clear technical documentation and reviews.

Requirements

Must-have technical skills and experience:

• Hands-on experience with STA tools such as PrimeTime and/or Tempus.
• Proven experience driving timing convergence at chip and hard-macro levels; knowledge of CTS, timing constraints, latch transparency, 0-cycle and multi-cycle path handling, and AOCV/POCV concepts.
• Proficient in scripting for EDA tool automation (TCL, Perl, Python; Awk is useful).
• Familiarity with digital backend implementation flows and tools (ICC/ICC2, Innovus) and RTL-to-GDS implementation flow.
• Experience with circuit simulation and process enablement tools (Hspice/FineSim, Monte Carlo) and correlation to STA.
• Strong technical writing and cross-team communication skills.

Nice-to-have / Preferred:

• 5–10 years of STA/timing experience on advanced technology nodes.
• In-depth knowledge of crosstalk, signal integrity, layout parasitic extraction, and feed-through handling.
• Basic device physics understanding and silicon-to-spice model correlation experience.

Education Requirements

Bachelor's, Master's (MTech/MS), or PhD in Computer Science, Electrical/Electronics Engineering, Microelectronics, VLSI, or a related engineering field. The posting specifies B.Tech/MTech/MS as acceptable. Experience guidance tied to degree: Bachelor's + ~2+ years experience, Master's + ~1+ year, or PhD (no specific years listed).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.