NPU Design Verification Sr Lead Engineer

Job Title

NPU Design Verification Sr Lead Engineer

Role Summary

Lead design verification for Qualcomm DSP/NPU IP, delivering verification environments, test plans, and automation to ensure IP and subsystem quality. Work closely with architecture, implementation, power, post-silicon and backend teams to drive verification from IP through SoC-level integration.

Experience Level

Senior - role targets experienced verification engineers; typically requires 5+ years in design verification of complex processor/DSP/NPU or ASIC IP.

Responsibilities

Accountabilities include ownership of verification strategy, implementation, and debug across IP and subsystem levels.

• Define and drive verification plans and coverage goals for DSP/NPU IP.
• Architect, implement and maintain SystemVerilog/UVM testbench infrastructure.
• Develop verification methodologies and automation to improve quality and efficiency.
• Execute simulations; debug functional failures at IP, subsystem and SoC levels.
• Perform gate-level simulation bring-up, timing-annotated and power-aware verification.
• Use assertions, formal/static property checking, HW–SW co-verification, emulation, and acceleration tools as appropriate.
• Collaborate with cross-functional teams (architecture, implementation, power, post-silicon, back-end) to close verification tasks.

Requirements

Must-have technical skills and experience for successful performance in this role; nice-to-have items listed separately.

• Must-have: Proven experience in processor/ASIC design verification and strong understanding of digital design and processor architecture.
• Must-have: Expertise in SystemVerilog/UVM testbench architecture and use of commercial simulators (Synopsys/Mentor/Cadence).
• Must-have: Proficiency in simulation-based debug and coverage-driven verification; experience with gate-level simulation and timing-aware verification.
• Must-have: Scripting and automation skills (Python, Shell, Perl, Makefiles) and experience building validation suites and automation frameworks.
• Nice-to-have: Experience writing C and assembly-level testcases and HW–SW co-verification.
• Nice-to-have: Exposure to power-aware verification using UPF and power-aware RTL verification techniques.
• Nice-to-have: Experience with formal methods, assertions, SystemC, and verification of processor subsystems.
• Strong analytical, debugging and communication skills; ability to work with global teams.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field are listed as acceptable. The posting specifies degree-plus-experience options: Bachelor's +3 years, Master's +2 years, or PhD +1 year in hardware engineering or related experience; equivalent practical experience is also referenced.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.