NPU/AI Processor Synthesis Sr Staff Engineer
QualcommJob Title
NPU/AI Processor Synthesis Sr Staff Engineer
Role Summary
Lead synthesis and timing-closure efforts for Neural Processing Unit (NPU) IP and subsystems in advanced SoCs. The role owns RTL-to-gate-level synthesis flows, PPA optimization, and cross-functional handoffs with RTL, STA and physical design teams.
Experience Level
Senior — role expects a seasoned synthesis engineer. Typical profile: 12+ years in ASIC synthesis and timing closure with at least 2 years focused on NPU or AI processor design. The posting also defines degree-based minimums (see Education Requirements).
Responsibilities
Drive synthesis and timing-quality-of-results for NPU IP and related subsystems; lead process and team-level activities.
- Lead RTL-to-gate-level synthesis using industry tools and maintain synthesis scripts and flows (hierarchical and flat).
- Drive pre-layout and post-layout timing closure across multiple voltage and process corners; resolve setup/hold issues with STA teams.
- Apply physical-aware synthesis and low-power strategies (UPF/CPF) to meet PPA targets.
- Validate and maintain SDC constraints for clocks, I/O, multi-cycle and false paths.
- Perform quality checks including LEC, clock/power checks and linting; coordinate DFT and physical-design handoffs.
- Investigate advanced synthesis methodologies and EDA tool capabilities to improve QoR.
- Mentor junior engineers and promote synthesis best practices across the team.
Requirements
Must-have technical skills and experience for immediate contribution; preferred items listed separately.
- 12+ years in ASIC synthesis and timing closure; minimum 2 years of experience on NPU or AI processor designs.
- Strong understanding of the ASIC flow: RTL → synthesis → STA → P&R and hands-on QoR ownership.
- Proficiency with synthesis and STA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime).
- Experience with low-power design flows (UPF/CPF) and multi-voltage designs.
- Advanced scripting skills (Tcl, Perl, Python) for automation of flows.
- Familiarity with EDA verification and analysis tools (Spyglass, lint, CDC, power analysis).
- Proven ability to lead synthesis teams and coordinate cross-functional engineering workstreams.
- Preferred: experience with advanced technology nodes (5nm/3nm), hierarchical and physical-aware synthesis, and prior tape-out experience for NPU or DSP cores.
Education Requirements
Degrees and experience alternatives listed in the posting: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of relevant work experience; OR Master's in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of relevant experience; OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of relevant experience. Fields specified: Computer Science, Electrical/Electronics Engineering, Computer Engineering or related technical fields.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
