NPU/AI Processor Synthesis Lead
QualcommJob Title
NPU/AI Processor Synthesis Lead
Role Summary
Lead synthesis and timing-closure activities for Neural Processing Unit (NPU) IP and subsystems in advanced SoCs. Drive synthesis flows, optimize for performance, power and area (PPA), and coordinate with architecture, RTL, STA and physical-design teams to produce high-quality gate-level netlists for advanced process nodes.
Experience Level
Senior. Typical minimum experience depends on academic qualification: generally 3+ years (Bachelor's), 2+ years (Master's), or 1+ year (PhD) of relevant hardware engineering experience.
Responsibilities
Deliver synthesis, timing closure and related flows for NPU IP and subsystems; mentor engineers and drive cross-functional handoffs.
- Own RTL-to-gate-level synthesis for NPU IP and subsystems using industry EDA tools.
- Develop and maintain synthesis scripts and hierarchical/flat synthesis flows.
- Drive pre-layout and post-layout timing closure across voltage/process/temperature corners.
- Collaborate with STA teams to identify and resolve setup/hold violations.
- Apply physical-aware synthesis and low-power (UPF/CPF) techniques to meet PPA targets.
- Validate and maintain SDC constraints: clocks, I/O delays, multi-cycle and false paths.
- Perform quality checks such as LEC, clock/power checks, and linting.
- Explore synthesis methodology and EDA tool improvements; mentor junior engineers and promote best practices.
Requirements
Must-have technical skills and experience (concise):
- Hands-on RTL-to-gate synthesis experience for complex digital IP, including scripting and flow automation.
- Proficiency with synthesis tools (e.g. Synopsys Design Compiler, Cadence Genus) and EDA tool flows.
- Proven experience driving timing closure (pre- and post-layout) and working with STA methodologies.
- Knowledge of low-power implementation flows (UPF/CPF) and physical-aware synthesis techniques.
- Experience creating and validating SDC constraints and resolving QoR issues with RTL and physical teams.
- Familiarity with LEC, clock/power checks, linting, and cross-team verification handoffs.
- Demonstrated ability to mentor engineers and collaborate across RTL, DFT, STA and physical design teams.
Nice-to-have:
- Experience with NPU/AI processor IP and advanced process nodes.
- Background in physical design-aware synthesis optimizations and advanced EDA automation.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting specifies minimum experience tied to degree: Bachelor's + 3+ years, Master's + 2+ years, or PhD + 1+ year of relevant hardware engineering experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
