NPU AI/Processor Synthesis Engineer - Sr Lead
QualcommJob Title
NPU AI/Processor Synthesis Engineer - Sr Lead
Role Summary
Senior synthesis engineer/technical lead on the NPU (Neural Processing Unit) design team responsible for RTL-to-GDS synthesis and timing closure for AI/ML accelerator IP and subsystems on advanced process nodes.
The role partners with Architecture, RTL, STA, DFT, and Physical Design teams to meet PPA targets and support tapeout activities.
Experience Level
Senior. The posting describes experience-equivalent degree options (see Education Requirements) and expects demonstrated synthesis and timing-closure experience.
Responsibilities
Key responsibilities include owning synthesis/QoR and driving timing closure from pre-layout to post-layout across modes and corners.
- Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
- Develop and maintain synthesis flows, constraints, and automation for hierarchical designs.
- Drive pre-layout and post-layout timing closure across multiple modes and process corners.
- Optimize designs for performance, power, and area using physical-aware synthesis methodologies.
- Create, validate, and maintain SDC timing constraints, clock definitions, false paths, and multi-cycle paths.
- Collaborate with RTL, DFT, STA, and Physical Design to resolve QoR, timing, power, and convergence issues.
- Perform quality checks including LEC, CDC, lint, and low-power verification.
- Analyze and improve synthesis QoR through scripting and flow enhancements; support tapeout activities.
Requirements
Must-have technical skills and experience; preferred items noted separately.
- Strong understanding of ASIC design flow from RTL to GDS and hands-on experience with RTL synthesis and timing closure.
- Experience developing timing constraints and signoff-quality SDCs, understanding of clocking architecture and timing concepts.
- Expertise with Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
- Strong timing analysis skills using PrimeTime or equivalent tools.
- Experience with low-power design methodologies and UPF-based flows.
- Proficiency in TCL and scripting languages such as Python or Perl to automate flows and analyze QoR.
- Excellent debugging, problem-solving, and cross-functional collaboration skills.
Nice-to-have:
- Experience on AI/ML accelerators (NPU), DSP, GPU, CPU, or other high-performance compute architectures.
- Familiarity with advanced process nodes (5nm, 4nm, 3nm and below) and physical-aware synthesis techniques.
- Experience with hierarchical design methodologies, LEC, CDC, lint, power analysis, and successful SoC or IP tapeouts.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, Engineering, or a related technical field. The posting allows equivalent practical experience in lieu of a degree and maps experience expectations to degree level (BSc +3 years, MSc +2 years, PhD +1 year).
For more information about Qualcomm careers, see Qualcomm contact.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
