NOC DV Staff Engineer

Job Title

NOC DV Staff Engineer

Role Summary

Verification Architect/Engineer responsible for design verification of infrastructure IPs (e.g., DDRSS, memory controllers) used in SoCs. The role owns IP-level DV environments, plans and implements verification flows, coordinates with design and SoC teams, and supports post-silicon debug and performance analysis.

Experience Level

Senior engineer (staff level). Typically requires multiple years of IP or hardware verification experience; see Education Requirements for degree-linked minimums.

Responsibilities

Primary responsibilities include ownership and execution of IP verification activities and cross-team coordination.

• Own DV testbench and verification collateral (checkers, trackers, scoreboards, assertions, functional coverage).
• Develop verification plans and test cases; drive code and functional coverage closure across stakeholders.
• Implement IP/cluster/formal verification flows and automation (Certitude, VC Formal, VPlan).
• Debug regression failures, identify and verify bug fixes; perform post-silicon root cause analysis with design, SW, and test teams.
• Coordinate with system architects, design, emulation, and SoC teams during IP development and bring-up.
• Support SoC-level performance modeling (latency, bandwidth) and quality sign-off documentation.

Requirements

Must-have technical skills and experience for effective performance in this role. Education details are summarized under Education Requirements and removed from these bullets to avoid duplication.

• 3+ years of IP verification or related experience; experience expectations vary by degree (see Education Requirements).
• Proven expertise with UVM-based verification and SystemVerilog testbench components (monitors, scoreboards, sequencers).
• Knowledge of ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Strong debugging, analytical, and problem-solving skills; experience debugging regressions and silicon issues.
• Ability to develop automation and validation scripts/tools; familiarity with verification tool flows.
• Effective communication and collaboration skills for working with a large, distributed design organization.

Nice-to-have:

• Experience with low-power design techniques (dynamic clock gating, memory/logic power collapse).
• Experience verifying designs to Automotive Safety Integrity Levels (ASIL).
• Proficiency in scripting (Python, Perl) and performance modeling languages (C/C++, SystemC).
• Post-silicon bring-up and HW–SW debug experience; familiarity with silicon debug toolchains.

Education Requirements

Degree options and equivalent experience: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering, Electronics & Communication, Microelectronics or related field with ~4+ years of relevant hardware/DV experience; OR Master's in those fields with ~3+ years; OR PhD with ~2+ years. The posting also indicates 3+ years of IP verification experience as a general expectation and allows related field or equivalent practical experience.

Contact: Qualcomm Careers

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.