NOC DV Sr Lead Engineer

Job Title

NOC DV Sr Lead Engineer

Role Summary

Responsible for verification architecture and implementation for next-generation infrastructure IPs (for example DDRSS and memory controllers) that go into SoCs. Plans and implements IP/cluster/formal verification flows, owns verification collateral, and coordinates with design, SoC, emulation, software and performance teams to drive quality sign-off.

Part of the Hardware Engineering group focused on IP verification, debug, and post-silicon validation.

Experience Level

Senior - typically requires around 8+ years in IP verification or related work. The posting provides degree-linked minimums (Bachelor's +3 years, Master's +2 years, PhD +1 year) and explicitly lists 8 years of IP verification experience for the senior qualification.

Responsibilities

Core responsibilities include ownership of verification assets, developing verification plans, and driving debug to closure.

• Own and maintain DV testbench and associated collaterals: checkers, trackers, scoreboards, assertions, and functional coverage.
• Develop test plans and testcases to cover design features and achieve code/functional coverage goals.
• Plan and implement IP/cluster/formal verification flows and coordinate with design and SoC teams through the IP development cycle.
• Debug regression signatures, perform root-cause analysis, and track bug fixes to closure.
• Collaborate with system architects, emulation, software, and performance teams on failure analysis and latency/bandwidth modeling.
• Deliver quality sign-off and required verification documentation.
• Develop and deploy scripts/tools for validation and automation (e.g., Certitude, VC Formal, VPlan).

Requirements

Must-have technical skills and experience. See nice-to-have list below.

• Proven experience in verification of infrastructure IPs (DDRSS, memory controllers) with IP-level ownership.
• Expertise in UVM-based verification and SystemVerilog for monitors, scoreboards and sequencers.
• Strong debugging, analytical and problem-solving abilities; experience with regression and silicon debug.
• Familiarity with ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Experience creating automation and validation scripts/tools (Python, Perl) and working with emulation/formal flows.
• Effective communication and collaboration across large, distributed design teams.

Nice-to-have:

• Experience with low-power design techniques (dynamic clock gating, memory power collapse).
• Experience verifying designs to Automotive Safety Integrity Levels (ASIL).
• C/C++/SystemC experience for performance modeling; post-silicon bring-up and silicon debug tool exposure.

Education Requirements

Posting references Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Micro Electronics or related engineering fields. It specifies degree-plus-experience combinations (Bachelor's +3 years, Master's +2 years, PhD +1 year) and otherwise cites ~8 years of IP verification experience for the senior role; equivalent practical experience is implied by the experience-based ranges.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.