NOC DV Senior Engineer

Job Title

NOC DV Senior Engineer

Role Summary

Verification architect/engineer responsible for planning and implementing design verification flows for infrastructure IPs (e.g., DDRSS, memory controllers) that integrate into SoCs. The role coordinates with IP and SoC design teams and supports bring-up and post-silicon debug.

Experience Level

Senior - typically expects mid-to-senior experience in IP verification. Source guidance indicates around 3+ years of IP verification or related experience; minimum qualifications allow varying years depending on degree.

Responsibilities

Core responsibilities include ownership of verification assets, test planning, debug, and documentation.

• Own DV testbench and verification collateral (checkers, trackers, scoreboards, assertions, functional coverage).
• Develop test plans and test cases to cover the feature set and drive coverage closure across testbench levels.
• Collaborate with system architects, design, emulation, and SoC teams on failure debug and coverage closure.
• Analyze regression signatures and identify required bug fixes.
• Provide quality sign-off and maintain verification documentation.
• Develop and deploy validation automation and tools (examples: Certitude, VC Formal, VPlan).
• Debug and root-cause post-silicon issues with design, software, and test teams.
• Work with SoC-level performance modeling teams on latency and bandwidth analysis.

Requirements

Must-have verification skills and tools experience; nice-to-have items listed separately.

• Must-have: Strong debugging, analytical and problem-solving skills specific to IP verification.
• Must-have: Expertise with UVM-based verification and SystemVerilog for monitors, scoreboards and sequencers.
• Must-have: Familiarity with ARM bus protocols, virtual memory concepts, and SoC system architecture.
• Must-have: Experience developing verification automation using scripting (Python/Perl) and familiarity with C/C++/SystemC for performance models.
• Must-have: Experience in IP verification (practical expectation: multiple years in IP/SoC verification and regression/debug workflows).

• Nice-to-have: Experience with low-power design techniques (dynamic clock gating, power collapse) and Automotive Safety Integrity Levels (ASIL).
• Nice-to-have: Post-silicon bring-up and HW-SW debug experience; exposure to silicon debug toolchains.
• Nice-to-have: Experience with formal/coverage tools and SoC performance analysis workflows.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics, or a related engineering field. Minimum-qualification variants in the source: Bachelor's + 2+ years experience, Master's + 1+ year experience, or PhD (years-of-experience expectations vary by degree). Equivalent practical experience may be considered where stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.