NOC Design Verification Sr Lead Engineer

Job Title

NOC Design Verification Sr Lead Engineer

Role Summary

Lead verification architect/engineer responsible for planning and executing IP and cluster verification for infrastructure IPs (memory controllers, DDR sub-systems) used in SoCs. Own the DV testbench, verification collateral, coverage closure, and coordinate debug with design, SoC, emulation and software teams throughout the development lifecycle.

Experience Level

Senior-level. The posting specifies degree-based minimum experience (see Education Requirements). Role expects multiple years of IP verification experience and proven ownership of verification flows and debug.

Responsibilities

Primary responsibilities include:

• Own DV testbench and verification collateral: checkers, trackers, scoreboards, assertions, functional coverage.
• Develop test plans and test cases to exercise design feature sets and drive code/functional coverage closure.
• Plan and implement IP/cluster/formal verification flows and verification infrastructure.
• Coordinate with system architects, design, emulation, and SoC teams on failure debug and closure activities.
• Analyze regression failures, identify root causes and track bug fixes to resolution.
• Develop and deploy validation scripts/tools (examples: Certitude, VC Formal, VPlan) to automate verification tasks.
• Participate in post-silicon debug and collaborate with SW and test teams to resolve silicon issues.
• Prepare quality sign-off artifacts and required verification documentation.

Requirements

Must-have and preferred skills for this role.

• Must-have: Strong debugging, analytical and problem-solving skills; expertise in UVM-based verification.
• Experience developing monitors, scoreboards, sequencers using SystemVerilog/UVM and scripting to accelerate verification.
• Knowledge of ARM bus protocols, virtual memory concepts and SoC system architecture.
• Experience with regression debug, coverage analysis, and verification closure processes.
• Experience developing/deploying verification scripts and tools; familiarity with formal tools and verification planning.
• Effective communication and collaboration skills for working with a global design organization.
• Nice-to-have: Low-power design verification (clock gating, power collapse), ASIL/automotive safety verification experience, C/C++/SystemC for performance modeling, post-silicon bring-up and HW-SW debug, exposure to silicon debug toolchains.

Education Requirements

Degree and experience combinations specified: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Micro Electronics, Engineering, or related field with 3+ years of hardware/IP verification experience; OR Master's degree in those fields with 2+ years; OR PhD with 1+ year. The posting accepts related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.