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Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm
October 8, 2026
Full-time
On-site
San Diego, California, United States
$121,800 - $182,600 USD yearly
RTL Design Jobs, Level - Mid-Career

Job Title

Next-Gen System Cache ASIC Digital Design Engineer

Role Summary

Design and validate RTL for SOC interconnects, cache and memory controller blocks as part of an ASIC engineering team. Work across micro-architecture, RTL implementation, verification, and silicon bring-up to meet performance, power and cost targets for Snapdragon-class SoCs.

Experience Level

Early-career to mid-level. The team welcomes recent graduates and engineers with several years of ASIC/RTL experience; specific minimums vary by degree (see Education Requirements).

Responsibilities

Primary responsibilities include micro-architecture, RTL development, verification and post-silicon debug for memory and interconnect subsystems.

  • Micro-architect and specify new-generation cache, memory subsystem and interconnect IP.
  • Implement RTL (Verilog/SystemVerilog) for modules and blocks according to architecture and specs.
  • Perform synthesis-aware design and low-power implementation optimizations.
  • Develop and execute verification and debug activities across the project lifecycle.
  • Evaluate hardware feasibility of algorithms and trade-offs for performance, power and cost.
  • Optimize clocking and silicon cost; troubleshoot silicon issues during bring-up.

Requirements

Required skills and experience for effective contribution on this role.

  • Practical experience or coursework in Verilog/SystemVerilog RTL design.
  • Familiarity with synthesis flows (Synopsys or equivalent) and synthesis-aware coding.
  • Experience with low-power design techniques and power-aware implementation concepts.
  • Verification experience including test plan development and coverage-based verification.
  • Proficiency in C/C++ and/or Python for tooling, validation and test automation.
  • Understanding of computer architecture, computer arithmetic, CPU/cache controller design is strongly desirable.
  • Good communication skills and ability to work effectively in a cross-functional team.
  • Prior ASIC design and design verification (DV) experience is a plus.

Education Requirements

Degree preference: Bachelor's, Master’s or PhD in Computer Engineering, Computer Science, Electrical Engineering, Science, Engineering or a related technical field. The posting specifies equivalence between degree and experience (e.g., Bachelor's + 2 years, Master's + 1 year, or PhD). Graduate GPA > 3.5 is noted as preferred for some degree lines. Equivalent practical experience is acceptable where specified.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-08