Senior Full-Chip RTL Integration Engineer

Job Title

Senior Full-Chip RTL Integration Engineer

Role Summary

Integrate complex internal and third-party IPs and subsystems into large-scale ASIC/SoC designs, owning top-level connectivity, clocking, reset, address mapping, and power domain integration. Collaborate with Architecture, RTL Design, Verification, DFT, and Physical Design teams to ensure design quality, verification readiness, testability, and successful signoff.

Experience Level

Senior-level. Role expects an experienced engineer with significant independent ownership of full-chip RTL integration and system-level verification workflows.

Responsibilities

The primary responsibilities focus on full-chip RTL integration, verification readiness, DFT integration, and automation to support design closure.

• Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, including top-level connectivity, clocking/reset architecture, address mapping, and power domain integration.
• Coordinate system-level integration activities with Architecture, RTL Design, Verification, DFT, and Physical Design teams.
• Perform RTL quality checks such as lint, CDC, RDC, synthesis, and connectivity validation.
• Develop and execute integration-level verification plans using SystemVerilog/UVM; debug simulation failures and support functional coverage closure.
• Collaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, ATPG and review fault-coverage metrics and testability reports.
• Support design signoff activities and ensure smooth handoff across implementation stages.
• Develop automation and scripting solutions to improve integration, verification, and debug productivity.

Requirements

Must-have technical skills and proven hands-on experience relevant to full-chip RTL integration and testability.

• Proven experience in ASIC/SoC RTL integration and top-level integration ownership.
• Deep knowledge of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols.
• Hands-on verification experience with SystemVerilog and UVM and ability to verify block- and integration-level designs independently.
• Strong understanding of DFT methodologies and practical experience with Scan, ATPG, MBIST, LBIST, JTAG, and test-compression techniques.
• Experience with lint, CDC, RDC, synthesis flows, and design-quality signoff processes.
• Strong debugging, analytical, and problem-solving skills; effective cross-team communication.

Nice-to-have:

• Experience with large-scale full-chip integration, high-speed interfaces, processor subsystems, memory controllers, and third-party IPs.
• Familiarity with Synopsys, Cadence, or Siemens DFT and verification tools.
• Experience with low-power design methodologies and UPF.
• Proficiency in Python, Perl, Tcl, or shell scripting and interest in automation or AI-assisted tooling.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is listed; the posting also accepts equivalent practical experience in lieu of a degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.