Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Job Title

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Role Summary

Design and micro-architect RTL blocks for SOC interconnects, caches and memory subsystems, and participate in power and system-level design for high-performance SoC platforms. Work with cross-functional teams through design, verification, silicon bring-up and debugging.

Experience Level

Mid-level — the team seeks candidates with approximately 3+ years of relevant ASIC design or verification experience (see Minimum Qualifications for alternative degree/experience mixes).

Responsibilities

Primary responsibilities for this role include micro-architecture, RTL design and validation, verification support, and silicon debugging for memory and interconnect subsystems.

• Micro-architect and specify new-generation SOC interconnect, cache and memory subsystem modules.
• Develop and implement RTL for assigned modules (Verilog/SystemVerilog).
• Perform synthesis-aware RTL development and work with synthesis tools/flows.
• Create and execute verification and test plans; perform coverage-based verification.
• Optimize designs for performance, power, area and cost; improve clock speed and low-power behavior.
• Debug pre-silicon and silicon issues; support bring-up and integration activities.
• Evaluate hardware feasibility of complex algorithms and system requirements.
• Collaborate with cross-functional teams and document micro-architecture and design specifications.

Requirements

Must-have skills and experience required to perform the role; additional desirable skills are listed separately.

• Practical experience with Verilog or SystemVerilog and RTL implementation for ASICs.
• Experience with synthesis flows and tools (Synopsys or equivalent) and synthesis-aware coding.
• Experience in low-power design techniques and power-aware RTL practices.
• Experience developing verification/test plans and using coverage-driven verification methodologies.
• Prior ASIC design, verification, validation, integration, or silicon bring-up experience.
• Strong debugging skills for pre-silicon and silicon failures; ability to troubleshoot complex SoC issues.
• Good written and verbal communication skills; ability to work in a team.

Nice-to-have:

• Experience designing RTL for CPU or cache controller blocks, or memory controller IP.
• Background in computer architecture or computer arithmetic.
• Familiarity with C/C++ or Python for scripts, testbench or tooling support.

Education Requirements

Bachelor's, Master’s, or PhD in Computer Engineering, Computer Science, Electrical Engineering or a related field are cited. The posting specifies GPA > 3.5 for Bachelor's and Master's in one qualifications section. Minimum qualifications provide alternate degree/experience combinations: Bachelor's + 4+ years relevant ASIC experience, Master's + 3+ years, or PhD + 2+ years. Equivalent practical experience is accepted per those minimum-qualification rules.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.