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Next-Gen, High-Speed HBM/LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm
September 07, 2026
Full-time
On-site
San Diego, California, United States
$140,000 - $229,800 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

Next-Gen, High-Speed HBM/LPDDR Memory Controller ASIC Digital Design Engineer

Role Summary

Design and deliver front-end memory and cache controller logic (HBM/LPDDR/DDR) for high-speed QCT SoCs. Work on architecture, RTL implementation, verification support, timing closure, and integration with CPU/GPU/DSP/multimedia subsystems.

Experience Level

Senior-level. Typical background: 5+ years ASIC/RTL front-end digital design and 3+ years hardware architecture experience; experience with high-speed (1+ GHz) designs preferred.

Responsibilities

Deliver architecture and RTL for next-generation memory controllers and support integration into SoCs.

  • Define micro-architecture and design specifications for memory/cache controller blocks.
  • Implement RTL, perform code reviews, and own design delivery.
  • Collaborate with verification teams and support verification strategy.
  • Perform synthesis, timing closure, and support physical design flow.
  • Run gate-level simulations and power analysis; debug at block and chip integration levels.
  • Provide integration/debug support with CPU/GPU/DSP/multimedia subsystems.
  • Contribute to design methodology and productivity improvements.

Requirements

Core technical skills and domain experience required or strongly preferred.

  • 5+ years ASIC design experience with RTL coding and front-end digital design.
  • 3+ years hardware architecture experience (front-end/SoC interfacing).
  • Experience with high-speed digital design, timing closure, and synthesis flows.
  • Hands-on experience with LPDDR memory and cache controller front ends and NoC-based interfaces to CPUs/DSPs/multimedia processors.
  • Familiarity with ordering of memory transactions to meet ISA requirements and with x86 or ARM CPU/bus architectures.
  • Debugging experience at RTL and integration levels; support for gate-level simulation and power analysis.
  • Nice-to-have: exposure to HBM designs, on-chip SRAM/L3 cache controller architecture, and RTL verification flows.

Education Requirements

The posting references degree-plus-experience options and an explicit preference for advanced technical degrees. Accepted backgrounds include a Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, Science, Engineering, or a related technical field with corresponding ASIC experience (examples from posting: Bachelor's + ~4 years experience; Master's + ~3 years; PhD + ~2 years). The posting also explicitly lists a Master's in Computer Engineering and/or Electrical Engineering as required/preferred for the role.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-06