New Grad ASIC RTL Design Engineer — Physical AI Compute

Job Title

New Grad ASIC RTL Design Engineer — Physical AI Compute

Role Summary

Contribute to the design and implementation of ASIC/SoC components for Xcelerium's real-time Physical AI compute platform. The role covers architecture exploration, microarchitecture, RTL design and verification, and physical-design feedback toward production silicon.

On-site in Irvine (alternate Santa Clara). Work with computer architects and chip designers on low-latency, high-performance embedded compute for autonomy and edge AI.

Experience Level

Entry-level / New graduate. Targeted at seniors or recent graduates; early-career engineers (hiring for candidates graduating by June 2026).

Responsibilities

Hands-on engineering across RTL, verification and implementation phases of ASIC/SoC development.

• Design and implement synthesizable RTL in SystemVerilog or Verilog.
• Translate workload requirements into hardware datapaths, control logic, memory systems, and interconnects.
• Perform simulation, debug, lint, CDC checks, synthesis, static timing analysis, and power analysis; act on physical-design feedback.
• Participate in verification activities: test plans, assertions, observability, and debug.
• Evaluate trade-offs for latency, throughput, power, area, timing, programmability, and reliability.
• Produce design documentation, interface specifications, implementation notes, and debug summaries; participate in design reviews.

Requirements

Core skills and attributes required. Education details are summarized in the Education Requirements section below.

• Must-have: Strong fundamentals in digital logic, synchronous design, finite state machines, pipelining, timing, and computer architecture.
• Must-have: Hands-on RTL experience writing Verilog or SystemVerilog through coursework, projects, internships, FPGA work, or ASIC projects.
• Must-have: Ability to write scripts or software in at least one language such as Python, C, or C++; strong debugging skills and careful hardware reasoning.
• Must-have: Clear written and verbal communication, ability to document design intent and explain technical tradeoffs, and high ownership.
• Nice-to-have: Experience with CPU/accelerator/memory subsystems, cache controllers, DMA, NoC, bus fabrics, or high-performance datapath design.
• Nice-to-have: Familiarity with RISC-V/ARM/MIPS ISAs, ASIC/FPGA flows (UVM, assertions, STA, P&R feedback), hardware construction languages (Chisel, Bluespec), or formal/constrained-random verification.
• Nice-to-have: Experience with Git, Linux, shell scripting, Make/CMake, EDA automation, tapeout, or open-source hardware projects.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred; equivalent hands-on project or internship experience accepted. Targeted at seniors/new graduates (latest graduation June 2026). Minimum GPA: 3.5. Open to candidates on CPT/OPT; US work authorization required.

About the Company

Company: Xcelerium

Headquarters: Irvine, CA, USA

Xcelerium is developing a compute platform and advanced ASIC/SoC technology for real-time Physical AI—systems that process rich sensor data and make decisions under tight constraints of latency, power, size, and reliability. Their work targets applications such as autonomous systems, robotics, wireless infrastructure, aerospace and defense, industrial automation, and edge AI.